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PDF PDUSBD12PWDH Data sheet ( Hoja de datos )
| Número de pieza | PDUSBD12PWDH | |
| Descripción | nullUSB interface device with parallel bus | |
| Fabricantes | NXP Semiconductors | |
| Logotipo |  |
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INTEGRATED CIRCUITS
PDIUSBD12
USB interface device with parallel bus
Product specification
Supersedes data of 1998 Sep 24
1999 Jan 08
Philips
Semiconductors
1 page  
Philips Semiconductors
USB interface device with parallel bus
Product specification
PDIUSBD12
DMA TRANSFER
Direct Memory Address (DMA) allows an efficient transfer of a block
of data between the host and the local shared memory. Using a
DMA controller, data transfer between the PDIUSBD12 main
endpoint (endpoint 2) and the local shared memory can happen
autonomously without local CPU intervention.
Preceding any DMA transfer, the local CPU receives from the host
the necessary setup information and programs the DMA controller
accordingly. Typically, the DMA controller is setup for demand
transfer mode and the byte count register and the address counter
are programmed with the right values. In this mode, transfers occur
only when the PDIUSBD12 requests them and terminated when the
byte count register reaches zero. After the DMA controller has been
programmed, the DMA enable bit of the PDIUSBD12 is set by the
local CPU to initiate the transfer.
The PDIUSBD12 can be programmed for single cycle DMA or burst
mode DMA. In single cycle DMA, the DMREQ is deactivated for
every single acknowledgement by the DMACK_N before being
asserted again. In burst mode DMA, the DMREQ is held active for
the number of bursts programmed in the device before returning
inactive. This process continues until the PDIUSBD12 receives a
DMA termination notice through EOT_N. This will generate an
interrupt to notify the local CPU that DMA operation is completed.
For DMA read operation, the DMREQ will only be activated
whenever the buffer is full signifying that the host has successfully
transferred a packet to the PDIUSBD12. With the double buffering
scheme, the host can start filling up the second buffer while the first
buffer is being read out. This parallel processing increases effective
throughput. For the case when the host does not fill up the buffer
completely (less than 64 bytes or 128 bytes for single direction ISO
configuration), the DMREQ will be deactivated at the last byte of the
buffer regardless of the current DMA burst count. It will be asserted
again on the next packet with a refreshed DMA burst count.
Similarly, for DMA write operation, the DMREQ remains active
whenever the buffer is not full. When the buffer is filled up, the
packet is sent over to the host on the next IN token and DMREQ will
be reactivated if the transfer was successful. Also, the double
buffering scheme here will improve throughput. For non-isochronous
transfer (bulk and interrupt), the buffer needs to be completely filled
up by the DMA write operation before the data is sent to the host.
The only exception is at the end of DMA transfer when the reception
of EOT_N will stop DMA write operation and the buffer content will
be sent to the host on the next IN token.
For isochronous transfer, the local CPU and DMA controller has to
guarantee that they are able to sink or source the maximum packet
size in one USB frame (1 ms).
The assertion of DMACK_N will automatically selects the main
endpoint (endpoint 2) regardless of the current selected endpoint.
The DMA operation of the PDIUSBD12 can be interleaved with
normal I/O access to other endpoints.
DMA operation can be terminated by resetting the DMA enable
register bit or the assertion of EOT_N together with DMACK_N and
either RD_N or WR_N.
PDIUSBD12 supports DMA transfer in a single address mode and it
can also work in dual address mode of the DMA controller. In the
single address mode, DMA transfer is done via the DREQ,
DMACK_N, EOT_N, WR_N and RD_N control lines. In the dual
address mode, DMREQ, DMACK_N and EOT_N are NOT used,
instead CS_N, WR_N and RD_N control signals are used. The I/O
mode Transfer Protocol of PDIUSBD12 needs to be followed. The
source of the DMAC is accessed during the read cycle, and the
destination accessed during the write cycle. Transfer needs to be
done in two separate bus cycles, storing the data temporarily in the
DMAC.
ENDPOINT DESCRIPTION
The PDIUSBD12 endpoints are generic enough to be used by
various device classes ranging from Imaging, Printer, Mass Storage
and Communication device classes. The PDIUSBD12 endpoints can
be configured for 4 modes depending on the “Set Mode” command.
The 4 modes are:
Mode 0 (Non-ISO Mode): no Isochronous transfer
Mode 1 (ISO-OUT Mode): Isochronous output only transfer
Mode 2 (ISO-IN Mode):
Isochronous input only transfer
Mode 3 (ISO-IO Mode):
Isochronous input and output transfer
1999 Jan 08
5
5 Page 
Philips Semiconductors
USB interface device with parallel bus
Product specification
PDIUSBD12
INTERRUPT MODES
Bit 7 of
Clock Division Factor
SOF_ONLY
interrupt mode
Bit 5 of
SetDMA
INTERRUPT_PIN
mode
Types
of
Interrupt
0
0
Normal
Interrupt1
0
1
Normal Interrupt
+ SOF1
1
X
SOF interrupt
ONLY
NOTE:
1. Normal Interrupt: Normal interrupts from Interrupt Register :
Data Flow Commands
Data flow commands are used to manage the data transmission
between the USB endpoints and the external microcontroller. Much
of the data flow is initiated via an interrupt to the microcontroller. The
microcontroller utilizes these commands to access and determine
whether the endpoint FIFOs have valid data.
Read Interrupt Register
Command
: F4h
Data
: Read 2 bytes
Interrupt Register Byte 1
76 54 32 1 0
00 00 0000
POWER ON VALUE
CONTROL OUT ENDPOINT
CONTROL IN ENDPOINT
ENDPOINT 1 OUT
ENDPOINT 1 IN
MAIN OUT ENDPOINT
MAIN IN ENDPOINT
BUS RESET
SUSPEND CHANGE
SV00864
Interrupt Register Byte 2
This command indicates the origin of an interrupt. The endpoint
interrupt bits (bits 0 to 5) are cleared by reading the endpoint last
transaction status register through Read Last Transaction Status
command. The other bits are cleared after reading the interrupt
registers.
76 54 32 1 0
XX XX XX X0
POWER ON VALUE
DMA EOT
RESERVED
SV00865
Bus Reset
Suspend Change
DMA EOT
After a bus reset an interrupt will be
generated this bit will be ‘1’. A bus reset
is identical to a hardware reset through
the RESET_N pin with the exception that
a bus reset generates an interrupt
notification and the device is enabled at
default address 0.
When the PDIUSBD12 did not receive 3
SOFs, it will go into suspend state and
the Suspend Change bit will be high. Any
change to the suspend or awake state
will set this bit high and generate an
interrupt.
This bit signifies that DMA operation is
completed.
Select Endpoint
Command
: 00-05h
Data
: Optional Read 1 byte
The Select Endpoint command initializes an internal pointer to the
start of the Selected buffer. Optionally, this command can be
followed by a data read, which returns this byte.
76 54 32 1 0
XX XX XX 0 0
POWER ON VALUE
FULL/EMPTY
STALL
RESERVED
Full/Empty
Stall
SV00866
A ‘1’ indicates the buffer is full, ‘0’
indicates an empty buffer.
A ‘1’ indicates the selected endpoint is in
the stall state.
1999 Jan 08
11
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