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PDSP16515A Schematic ( PDF Datasheet ) - Mitel Networks Corporation

Teilenummer PDSP16515A
Beschreibung Stand Alone FFT Processor
Hersteller Mitel Networks Corporation
Logo Mitel Networks Corporation Logo 




Gesamt 27 Seiten
PDSP16515A Datasheet, Funktion
DS3922
PDSPP1DS6P51165515AA
Stand Alone FFT Processor
Advance Information
Issue 2.0
April 1999
Features
q Completely self contained FFT Processor
q Pin and functionally compatible with the
PDSP16510A
q Expanded width internal RAM supports up to 1024
complex points
q 18 bit internal data bus with block floating point
arithmetic for increased dynamic range
q 500 MIP operation gives 87 microsecond
transformation times for 1024 points
q Up to 45MHz sampling rates with multiple devices.
q Up to 85dB noise rejection
q A choice of internal window operators with no
external ROM provide up to 67dB side lobe
attenuation.
q 84 pin PGA or 132 pin surface mount package
Associated Products
PDSP16330 Pythagoras Processor.
PDSP16256 Programmable FIR Filter.
PDSP16350 I/Q Splitter / NCO
PDSP16510A Stand Alone FFT Processor
The PDSP16515A performs Forward or Inverse Fast
Fourier Transforms on complex or real data sets
containing up to 1024 points. Data and coefficient input
are both represented by 16 bits. Data is expanded
internally to 18 bits and subject to Block Floating Point
arithmetic to preserve a greater dynamic range.
An internal RAM is provided which can hold up to 1024
complex data points. This removes the memory transfer
bottleneck, inherent in building block solutions. Its
organisation allows the PDSP16515A to
simultaneously input new data, transform data stored in
the RAM, and to output previous results. No external
buffering is needed for transforms containing up to 256
points, and the PDSP16515A can be directly connected
to an A/D converter to perform continuous transforms.
The user can choose to overlap data blocks by either
0%, 50%, or 75%. Inputs and outputs are synchronous
to the 45MHz system clock used for internal operations.
Ordering Information
PDSP16515A C0 AC
( Commercial - PGA
Package )
PDSP16515A C0 GC
( Commercial - Leaded
Chip Carrier )
PDSP16515A B0 AC
( Industrial - PGA
Package )
PDSP16515A B0 GC
( Industrial - Leaded
Chip Carrier )
PDSP16515A A0 AC
( Military - PGA
Package )
PDSP16515A A0 GC
( Military - Leaded Chip
Carrier )
PDSP16515A/MA/GCPR ( Military - Screened
Leaded Chip Carrier. See separate datasheet for
details )
A 1024 point complex transform can be completed in
some 87µs, which is equivalent to throughput rates of
500 million operations per second. Multiple devices can
be connected in parallel in order to increase the
sampling rate up to the 45MHz system clock. Six
devices are needed to give the maximum performance
with 1024 point transforms.
Either a Hamming or a Blackman-Harris window
operator can be internally applied to the incoming real or
complex data. The latter gives 67dB side lobe
attenuation. The operator values are calculated
internally and do not require an external ROM nor do
they incur any time penalty.
The increased internal bus size together with block
floating arithmetic produce up to 85dB of noise
rejection.
The device outputs the real and imaginary components
of the frequency bins. These can be directly connected
to the PDSP16330 in order to produce magnitude and
phase values from the complex data.
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PDSP16515A Datasheet, Funktion
PDSP16515A
subsequent passes a Control Register Bit allows the user to
continue to select these 18 bits, or instead to use the 18 most
significant bits. The latter option is equivalent to a 3 bit word
growth. The 2 or 3 bit word growth option applies to ALL
subsequent passes and is not a per pass option.
If the 2 bit option is selected there is a possibility of overflow
occurring in one of the passes. The prediction of overflow is
mathematically difficult, and only occurs with specific complex
square waves. Scaling down the inputs cannot be guaranteed
to prevent overflow because of the block floating point shifting
scheme, which is discussed later. Overflow can NEVER occur
if the 3 bit option is chosen, but at the expense of worse
dynamic range.
When overflow does occur a flag is raised which can be read
by the user ( see later discussion on scale tag bits ), and the
results ignored. In addition all frequency bins are forced to
zero to prevent any erroneous system response.
Even with only 2 bit word growth poor dynamic range can
result and becomes worse when the incoming data does not
fully occupy all the bits in the word. These problems are
overcome in the PDSP16515A, however, by a block floating
point scheme which compensates for any unnecessary word
growth.
During each pass the number of sign bits in the largest result
is recorded. Before the next pass, data is shifted left [multiplied
by 2], once for every extra sign bit in this recorded sample. At
least one component in the block then fully occupies the 18 bit
word, and maximum data accuracy is preserved
Up to four shifts are possible before every pass after the first,
with a total of fifteen for the complete transform. At the end of
the transform the number of left shifts that have occurred is
indicated on S3:0. Lack of pins prevents a separate output
being available to indicate that overflow has occurred in the 2
bit word growth option. For this reason the maximum number
of compensating left shifts in this mode is restricted to 14.
State 15 is then used to indicate that overflow has occurred.
The first step in the butterfly calculation multiplies 18 bit data
values with 16 bit sine/cosine values, to give 18 bit results.
WORKSPACE
A
INPUT
DATA
LOAD
WORKSPACE
B
TRANS-
FORM
FFT
DATA PATH
O/P
BUFFER
LOAD IN
LAST PASS
Figure. 4. RAM Organization with 256 Data
Points
6
INPUT
DATA
TRANS-
FORM
WORKSPACE
LOAD
FFT
DATA PATH
OUTPUT
Figure 5. RAM Organization with 1024 Point
Transforms
This increased word length preserves accuracy through the
following adder network, and has been shown through
simulations to be an optimum size for transform sizes up to
1024 points. This is particularly true when the input data is
restricted to below 16 bits, as is necessary with practical A/D
converters with very high sampling rates. The bottom bit of this
18 bit word is forced to logical one and as such is a
compromise between truncation and true rounding. It gives a
lower noise floor in the outputs compared to simple truncation.
To prevent any possibility of overflow during the butterfly
calculation the word length is allowed to grow by one bit
through each of the three adders. The least significant bit is
always discarded in the first two adders . Eighteen bits arethen
chosen from the final adder in the manner discussed earlier,
and the number of sign bits in the largest result recorded for
use in the following pass.
Fig. 3 shows one of the four internal data paths which can
compute a radix-4 butterfly in twelve system clock cycles. This
equates to completing the butterfly in 3 cycles for the complete
device.
Data Transfers
The data transfer mechanism to and from the internal RAM
has been designed for use in a wide variety of applications.
The provision of an independent input strobe (DIS), allows
data to be loaded without the need for additional external
buffering. An independent output strobe (DOS) is also
provided. DIS and DOS can thus be tied together, this being
particularly useful when the device is performing the inverse
transform back to the time domain. Transfer of data occurs
internally from DIS to SCLK, so although thay can be of
different frequencies, they must be synchronous to each
other. In the same way transfer of data also occurs from SCLK
to DOS, so while DOS can also be independent of SCLK it
must also be synchronous to it. Inputs and outputs are both
supported by flag and enabling signals which allow transfers
to be properly co-ordinated with the internal transform
operation.
In many applications the DIS and DOS inputs can be tied
together and fed by the sampling clock. If the output rate must
be higher than the input rate, as with multiple devices
supporting overlapped data samples, both strobes can still be
connected together. The clock supplied should then be twice
or four times the sampling clock, and an internal divider can be
used to provide the correctly reduced input rate. The provision
of a separate DOS pin does, however, allow the output rate to
be different to the input rate, and therefore faster than strictly
needed. Further output processing at higher rates is then
possible if this is advantageous to system requirements.

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PDSP16515A pdf, datenblatt
PDSP16515A
Valid transformed data is actually available within the device
from DAV going active until INEN again goes active, and a
new set of data is loaded. The output tristate drivers, however,
normally go high impedance when DAV goes in-active once a
dump operation has been completed. In order to support
systems in which it may be necessary to read the transformed
data more than once, a Control Register Bit is provided which
keeps the DAV output active until a further INEN edge is
received. The user must then keep track of how many outputs
have been dumped before INEN is generated to start a new
load operation.
The DAV output can be delayed by an amount equivalent to
the pipeline delay through the PDSP16330. This option is
invoked by setting a control bit, and allows DAV to indicate that
polar data is available at the output of the PDSP16330. When
the option is used the tri-state outputs will be enabled when
data is actually available and DEN is active, and not when DAV
eventually goes active.
Two Control Register Bits allow a range of dump size options
to be supported. In some applications the results of interest
may only lie in the lower 25 or 50% of the frequency bins, the
sampling rate having been chosen to prevent aliasing, and the
transform size having been selected to give the required
frequency resolution. In other systems it is only necessary to
output the second half of a given sized transform. This is useful
when filtering is to be performed in the frequency domain using
Overlap /Discard Fast Convolutions. With this method FIR
filters with N taps can be implemented in the frequency domain
using 50% overlapped transforms on 2N samples. After
multiplication in the frequency domain with the required
frequency response, the inverse transform is performed and
the first half of each output is discarded. Since only half the
results are dumped, the dump clock need not be twice the rate
of the clock used to load data.
Full Co- Processor Operation
A single device can be configured as a co-processor to a host
system in which both the loading and dumping of data is under
the control of the host. Such a system is shown in Figure 6, in
which DEN is a host provided enable for host read operations,
and INEN is an enable for host write operations. DIS and DOS
are host data strobes.
The host loads a block of data into the PDSP16515A, using
DIS enabled by INEN, which is then automatically
transformed. The DAV output provides a flag indicating that
the transform is complete, and results are then read by the
host using DOS enabled by DEN. A new set of inputs is not
normally loaded until the previous results are complete. If,
however, 1024 point transforms are not to be performed,
loading new data could coincide with dumping previous
results. This, however, would require a host system with
separate input and output buses, and which also allowed
coincident transfers. As discussed previously, transferring
results must take no longer than loading new data to prevent
corruption of the outputs.
In the system illustrated by Figure 6, the host also controls the
mode of operation of the FFT processor. The DEF signal is
produced from an address decode, and the control
parameters are loaded from the host bus by connecting the
AUX inputs to the data outputs.
Real Only Transfprms With a Single Device
In the simplest case real transforms can, of course, be
computed by forcing zero levels on the imaginary input pins.
The device can, however, be configured to internally perform
two simultaneous real transforms instead of a single complex
transform. The block floating point logic will then use data from
both blocks when it determines the number of shifts to be
applied. This dual transform technique is used to increase the
maximum permissible sampling rates, but since an additional
data pass is required in order to un-scramble the transformed
data, the actual performance is not quite double that possible
with a complex transform of the same size. The 4 x 64 point
complex mode becomes an 8 x 64 real mode, but the change
from 16 x 16 complex transforms to 32 x 16 real transforms is
not supported.
When a real transform is performed the algorithm produces
complex results for each of the incoming data blocks, but each
result only represents the first half of the frequency domain
data. This does not cause any loss of information since the two
halves are mirror images of each other. As with complex
transforms, it is necessary for a different system configuration
to be used when 1024 point transforms are required. These
are considered later, and the following only applies to 256 or
64 point transforms.
In a single device system, performing non overlapped
transforms on data from a SINGLE source, only the Real input
pins are used, and the Imaginary inputs are redundant except
when configuring the device. By setting Control Register Bits
8:6 to 101, however, it is possible for a single device to accept
data from two independent sources using the real and
imaginary inputs. Maximum sampling rates will then only be
half those possible when a single source is used, if no
incoming data is to remain un-processed. With two sources a
transform must be completed in the time to load parallel
blocks, otherwise incoming data will be lost. With one source
a transform need not be finished until two data blocks have
been acquired. In this dual input mode results from data on the
real inputs always precede those from the imaginary inputs.
If block overlapping is needed, it is always necessary to load
pairs of data blocks simultaneously, using both the real and
imaginary inputs. With dual sources of data this presents no
problem, and Control Bits 8:6 should be set to 110 or 111 for
the relevant amount of overlapping. If data is from a single
source an external FIFO is needed to provide a simple delay
for a block of data. Decodes 001 through 100 from Control Bits
8:6 must be used to select the required overlap.
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