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PDSP16510A Schematic ( PDF Datasheet ) - Mitel Networks Corporation

Teilenummer PDSP16510A
Beschreibung Stand Alone FFT Processor
Hersteller Mitel Networks Corporation
Logo Mitel Networks Corporation Logo 




Gesamt 25 Seiten
PDSP16510A Datasheet, Funktion
PDSP1PD6S5P11605A10
Stand Alone FFT Processor
Supersedes version in December 1993 Digital Video & DSP IC Handbook, HB3923-1
DS3475 - 4.4 May 1996
The PDSP16510 performs Forward or Inverse Fast
Fourier Transforms on complex or real data sets containing up
to 1024 points. Data and coefficients are each represented by
16 bits, with block floating point arithmetic for increased
dynamic range.
An internal RAM is provided which can hold up to 1024
complex data points. This removes the memory transfer
bottleneck, inherent in building block solutions. Its organisa-
tion allows the PDSP16510 to simultaneously input new data,
transform data stored in the RAM, and to output previous
results. No external buffering is needed for transforms con-
taining up to 256 points, and the PDSP16510 can be directly
connected to an A/D converter to perform continuous trans-
forms. The user can choose to overlap data blocks by either
0%, 50%, or 75%. Inputs and outputs are synchronous to the
40MHz system clock used for internal operations.
A 1024 point complex transform can be completed in
some 98µs, which is equivalent to throughput rates of 450
million operations per second. Multiple devices can be con-
nected in parallel in order to increase the sampling rate up to
the 40MHz system clock. Six devices are needed to give the
maximum performance with 1024 point transforms.
Either a Hamming or a Blackman-Harris window operator
can be internally applied to the incoming real or complex data.
The latter gives 67dB side lobe attenuation. The operator
values are calculated internally and do not require an external
ROM nor do they incur any time penalty.
The device outputs the real and imaginary components of
the frequency bins. These can be directly connected to the
PDSP16330 in order to produce magnitude and phase values
from the complex data.
ASSOCIATED PRODUCTS
PDSP16540 Bucket Buffer
PDSP16330 Pythagoras Processor.
PDSP16256 Programmable FIR Filter.
PDSP16350 I/Q Splitter / NCO
DATA INPUT
3 TERM
WINDOW
OPERATOR
COEFFICIENT
ROM
WORKSPACE
RAM
WORKSPACE
RAM
FOUR
DATA PATHS
OUTPUT
BUFFER
RESULT OUPUT
Fig. 1. Block Diagram
FEATURES
Completely self contained FFT Processor
Internal RAM supports up to1024 complex points
16 bit data and coefficients plus block floating point for
increased dynamic range
450 MIP operation gives 98 microsecond transforma-
tion times for 1024 points
Up to 40MHz sampling rates with multiple devices.
Internal window operator gives 67dB side lobe
attenuation and needs no external ROM.
84 pin PGA or 132 surface mount package
SAMPLE
CLOCK
ANALOG
INPUT
CONFIGURATION
WORD
DIS
AUX15:0
GND
INEN DOS
R15:0
PDSP16510
A/D D15:0
I15:0
DEF DEN DAV S3:0
CLK
X
PDSP16330
Y
PHASE
MAGNITUDE
GND
RESET
SCALE VALUE
AVAILABLE
Fig. 2. Typical 256 Point Real Only System Performing Continuous Transforms
1






PDSP16510A Datasheet, Funktion
PDSP16510
noted that the amount of overlap between I/O transfers and
transforms is completely under the control of the system, since
an input enable signal (INEN) and an output enable (DEN) can
be used to initiate transfers.
In the 1024 point mode there is insufficient workspace for
input and output buffering in addition to working memory. The
device is then configured in a mode with separate load,
transform and dump operations. The internal arrangement is
shown in Fig. 5. The support of an external input buffer is
needed if incoming samples are not to be lost whilst a
transform is in progress. This is loaded at the sample clock
rate and transferred to the FFT processor as quickly as
possible. In this mode the PDSP16510 always expects to
receive 1024 words, regardless of the amount of block over-
lapping. Data stored internally cannot be re-used when block
overlapping is required, and data from the external buffer must
be re-read as necessary.
Fig. 6 illustrates a typical 1024 point system with an input
buffer which supports complex input data. The input buffer
can be provided by a PDSP16540 Bucket Buffer without the
need for any external control logic. It supplies RAM for 1024
x 32 complex words, and allows transfers to the FFT Proces-
sor at the full system clock rate. The PDSP16540 also sup-
ports the standard 50% and 75% data block overlapping, but
in addition allows the user to define the amount of overlap to
within 32 words.
If no incoming data is to remain un-processed, the user
must ensure that the time taken to acquire sufficient data to
instigate a new transform is greater than or equal to the
transformation time itself. The latter can be calculated from
Table 4, once the system clock rate has been defined. When
1024 point transforms are performed, both the time to read
data from the input buffer, and also the time to dump data,
must be included in the calculation to determine the minimum
time in which data can be loaded into the external buffer.
The peak transfer rate is limited by the characteristics of
the I/O circuits, but can be greater than the sampling rate
which is determined by the transform time. When load and
dump operations are not concurrent with transform operations
( as in the 1024 point modes ), then the maximum I/O rate is
equal to the system clock rate, Ø. When other transform sizes
are specified, the sampling rate, S, is reduced by a factor F.
This is defined below where Ø is in MHz and L is the system
clock low time in nanoseconds :
S = FØ, where F = 4 / (6+0.001ØL)
F is typically 0.66 and applies to all transforms except for those
of 1024 points, even if INEN is driven such that concurrent
operations do not actually occur (Note also that S must be
1
DIS
DATA IN
VALID
TSD
THD
INEN
TSA THA
LFLG
INEN
Edge activated
system
TFH
Min Time =THA
Characteristic
N/2
TSI THI
N1
N
50% Overlap
TFL
TFL
TFH
TED
16510A,A0,B0,C0
Symbol
Min Max
TSA
Units
Data In set up Time
Data In Hold Time
INEN active going set up
INEN active Hold Time
INEN in-active Hold Time to ensure no load
INEN in-active going set up for no load operation
Delay to LFLG going active ( 30 pf load )
Delay to LFLG going in-active ( 30 pf load )
Min time to INEN low in edge mode
TSD
THD
TSA
THA
THI
TSI
TFH
TFL
TED
10
0
8
0
2
8
10
10
15
Table 1. Advanced Timing Information with Continuous Inputs.
6
ns
ns
ns
ns
ns
ns
ns
ns
ns

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PDSP16510A pdf, datenblatt
PDSP16510
given previously.
The time taken to dump the transformed data must be no
more than the load time, if continuous inputs are to be
supported and I/O operations are concurrent with transforms.
With block overlapping the dump time must be reduced to the
time taken to load the partial block. This dump time must
include four extra DOS strobes needed to prime the output
circuitry when a transform is complete. These, in effect, can be
added to the transform time such that with concurrent I/O and
0%, 50%, or 75% overlapping;
nS or (nS)/2 or (nS)/4 must be gtr than or equal to PK + 4W
where n is the transform size, S is the input DIS period, P is
the number of clock periods given in Table 4, K is the system
clock period, and W is the DOS period which can be less than
S if necessary. Note also that S must be synchronous to
SCLK, and if an asynchronous ratio is required then a
pdsp16540 input buffer should be used.
When DIS and DOS are produced from a common source
the minimum allowable sampling period must be increased to
allow for the extra dumping time. Thus when DIS and DOS
have equal periods and, for example, there is no overlapping;
(n - 4)S must be greater than or equal to PK
The maximum sampling rates given in Table 5 allow for the
extra dumping time.
The load and dump operations are not concurrent with
transforms in the 1024 point modes, and an external input
buffer will be needed if loss of incoming data is to be avoided.
Complex Data
Input
Configuration
Parameters
Power on
Reset
Output
Clock
IMAG
PDSP16510
REAL
O/P
S
PDSP16330
CLK
MAG'
PHASE
IMAG
PDSP16510
REAL
O/P
S
IMAG
PDSP16510
REAL
O/P
S
SCALE
TAG
DATA
AVAIL'
INPUT CLOCK
Fig 9. Multiple Device Configuration
12
This is loaded at the sampling rate and then data is transferred
to the PDSP16510 at a user defined rate. The time taken to
load this external buffer must be at least equal to the sum of
the time to transfer data in and out of the FFT processor and
the transform time itself. When data blocks are overlapped by
50% or 75%, no more than one half or one quarter of the block,
respectively, must have been loaded in the same time. In the
1024 point modes the dump time can be any user defined
value, and need not be increased to allow for block overlap-
ping. The dump time, however , does directly effect the
maximum sampling rates which can be accommodated with-
out loss of incoming data.
The maximum sampling rates for 1024 point transforms
at any load and dump rate can be calculated from the following
relationship:
1024S or 512S or 256S > 1024B + PK + D
for 0%, 50%, or 75% overlapping respectively. S, P, and K
were defined opposite. B is the clock period in which data is
read from the input buffer and loaded into the device, D is the
total dump time allowing for the four extra DOS periods. The
periods of the load and dump clocks cannot be less than the
system clock period. The maximum sampling rates given in
Table 5 assume that a 40 MHz I/O rate is used, and that all
results are dumped.
MULTIPLE DEVICE SYSTEMS
In real time applications several devices may be used in
parallel in order to increase the sampling rate, but not to
increase the transform size. When all outputs are commoned
together, and feed a single output processor, then the data
dump time must always be less than or equal to the time taken
to load the data block ( or 50% or 25% of the time with block
overlapping ). In most configurations with block overlapping
the dump rate requirements will limit the maximum input rate,
if only one output processor is provided. This can be avoided
if the system provides separate output processors for every
device. The system clock used for internal calculations then
ultimately imposes a limit on the maximum sampling rate
possible.
A multiple device system performing complex transforms
with a single output processor is shown in Figure 9. The INEN/
LFLG signals are used to co-ordinate the segmentation of
data between devices. The in-active going edge of LFLG
instigates the load procedure in the next device, and, since
this edge can be programmed to occur either 25%, 50%, or
100% through the load operation, it can cause the next device
to commence loading before the previous one has finished. In
this manner data block overlapping is achieved. When mul-
tiple concurrent transforms are performed ( for example 4 x 64
or 8 x 64 ) two LFLG transitions are sometimes needed to
support block overlapping. This is fully explained in the section
on Mode 1 sampling rates.
In any of the multiple device modes an INEN edge
transition is needed to start a new load procedure when the
previous one has finished. When the LFLG output from the last
device is fed back to the INEN input of the first device,
continuous transforms will be executed. This continuous
sequence can be started by the rising edge of DEF if Control
Register Bit 12 is set in the first device (see section on Loading

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