PDSP16488GC Datasheet PDF - Mitel Networks Corporation
| Part Number | PDSP16488GC | |
| Description | Single Chip 2D Convolver with Integral Line Delays | |
| Manufacturers | Mitel Networks Corporation | |
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PDSP16488A
Single Chip 2D Convolver with Integral Line Delays
Advance Information
Supersedes version in 1996 Media IC Handbook, HB4599-1.0
and the PDSP16488A MA data sheet, DS3742
DS3713 - 6.4 December 1997
The PDSP16488A is a fully integrated, application specific,
image processing device. It performs a two dimensional convo-
lution between the pixels within a video window and a set of
stored coefficients. An internal multiplier accumulator array can
be multi-cycled at double or quadruple the pixel clock rate. This
then gives the window size options listed in Table 1.
An internal 32kbit RAM can be configured to provide either
four or eight line delays. The length of each delay can be
programmed to the users requirement, up to a maximum of 1024
pixels per line. The line delays are arranged in two groups,which
may be internally connected in series or may be configured to
accept separate pixel inputs. This allows interlaced video or
frame to frame operations to be supported.
The 8-bit coefficients are also stored internally and can be
downloaded from a host computer or from an EPROM. No
additional logic is required to support the EPROM and a single
device can support up to 16 convolvers.
The PDSP16488A contains an expansion adder and delay
network which allows several devices to be cascaded. Con-
volvers with larger windows can then be fabricated as shown in
Table 2.
Intermediate 32-bit precision is provided to avoid any danger
of overflow, but the final result will not normally occupy all bits.
The PDSP16488A thus provides a gain control block in the
output path, which allows the user to align the result to the most
significant end of the 32-bit word.
Pixel Window size Maximum pixel
size Width Depth rate (MHz)
Line delays
84
88
88
16 4
16 8
4
4
8
4
4
20
20
10
20
10
431024
431024
83512
43512
43512
Table 1 Single PDSP16488A configurations
COMPOSITE
DATA
PIXEL
CLOCK
GEN
SYNC
SYNC
EXTRACT
ODD FIELD
ADC
OPTIONAL
FIELD
DELAY
EPROM POWER
ON
ADDR DATA RESET
CLK
HRES
BYPASS
RES
DELOP
DELAYED
SYNC
PDSP16488A
L7:0 D15:0
OUTPUT
DATA
IP7:0
Fig. 1 Typical stand-alone real time system
FEATURES
s The PDSP16488A is a replacement for the
PDSP16488 (see Note below)
s 8 or 16-bit Pixels with rates up to 40 MHz
s Window Sizes up to 838 with a Single Device
s Eight Internal Line Delays
s Supports Interlace and Frame-to-Frame Operations
s Coefficients Supplied from an EPROM or Remote Host
s Expandable in both X and Y for Larger Windows
s Gain Control and Pixel Output Manipulation
s 84-pin PGA or 132-pin QFP Package Options
Note: PDSP16488A devices are not guaranteed to cascade with
PDSP16488 devices. Mitel Semiconductor do not recommend
that PDSP16488A be mixed with PDSP16488 devices in a single
equipment design. The PDSP16488A requires external pullup
resistors in EPROM Mode (see Static Electrical Characteristics).
Max.
pixel Pixel
No. of PDSP16488As for N3N window size
rate size
(MHz)
333 535 737 939 11311 15315 23323
10 8 1 1 1 4 4
10 16 1 2 2 - -
20 8 1 2 2 6 6
20 16 1 4 4 - -
40 8 1 4* 4* - -
40 16 2 - - - -
4
-
8
-
-
-
9
-
-
-
-
-
*Maximum rate is limited to 30MHz by line store expansion delays
Table 2 PDSP16488As needed to implement typical window sizes
ORDERING INFORMATION
Commercial (0°C to 170°C)
PDSP16488A / C0 / AC (PGA)
Industrial (240°C to 185°C)
PDSP16488A / B0 / AC (PGA)
PDSP16488A / B0 / GC (QFP)
Military (255°C to 1125°C)
PDSP16488A / A0 / AC (PGA)
PDSP16488A / A0 / GC (QFP)
PDSP16488A / MA / ACBR (PGA) MIL-STD-883 Class B*
PDSP16488A / MA / GCPR (QFP) MIL-STD-883 Class B*
*See Notes following Static Electrical CharacteristicsTable
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Pin Signal
A1 L0
B1 F1
C2 L1
C1 L2
D2 L3
D1 N/C
E2 L4
E1 L5
F2 L6
G2 L7
G1 IP7
H2 N/C
J1 IP6
J2 IP5
K1 IP4
K2 N/C
L1 IP3
Pin Signal Pin Signal Pin Signal
L2 IP2
M1 IP1
N1 IP0
N2 BYPASS
M3 X15
N3 X14
M4 X13
N4 N/C
M5 SINGLE
N5 X12
M6 X11
M7 MASTER
N7 X10
M8 X9
N9 X8
M9 X7
N10 X6
M10 X5
N11 X4
M11 X3
N12 X2
N13 X1
M13 X0
L12 DELOP
L13 PC0
K12 RES
K13 CS0
J12 CS1
J13 CS2
H12 CS3
G12 PROG
G13 DS
F12 CE
E13 R/W
E12 HRES
D13 OVR
D12 PC1
C13 BIN
C12 OEN
B13 D0
A13 D1
A12 D2
B11 D3
A11 D4
B10 D5
A10 D6
B9 D7
A9 D8
B8 CLK
B7 N/C
A7 D9
Table 4 Pin connections for AC84 (power) package. See Fig. 3a.
Pin Signal
B6 D10
A5 D11
B5 N/C
A4 D12
B4 D13
A3 D14
B3 D15
A2 F0
F1 VDD 1
N6 VDD 2
F13 VDD 3
A6 VDD 4
H1 GND1
N8 GND2
H13 GND3
A8 GND4
Pin
Signal Pin Signal
Pin
Signal
Pin
1 N/C
2 D0
3 OEN
4 BIN
5 PC1
6 VDD
7 GND
8 OVR
9 N/C
10 HRES
11 R/W
12 CE
13 N/C
14 N/C
15 GND
16 N/C
17 DS
18 GND
19 VDD
20 PROG
21 GND
22 CS3
23 CS2
24 CS1
25 CS0
26 VDD
27 RES
28 PC0
29 N/C
30 DELOP
31 X0
32 X1
33 N/C
34 N/C
35 X2
36 X3
37 X4
38 N/C
39 X5
40 GND
41 X6
42 X7
43 N/C
44 X8
45 X9
46 VDD
47 VDD
48 VDD
49 X10
50 MASTER
51 N/C
52 X11
53 X12
54 SINGLE
55 GND
56 GND
57 N/C
58 X13
59 X14
60 N/C
61 X15
62 VDD
63 BYPASS
64 IP0
65 VDD
66 N/C
67 N/C
68 IP1
69 GND
70 IP2
71 N/C
72 VDD
73 IP3
74 VDD
75 IP4
76 GND
77 IP5
78 GND
79 IP6
80 VDD
81 IP7
82 VDD
83 N/C
84 L7
85 GND
86 L6
87 GND
88 L5
89 VDD
90 L4
91 VDD
92 L3
93 VDD
94 L2
95 GND
96 L1
97 F1
98 L0
99 N/C
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
Table 5 Pin connections for GC132 (power) package. See Fig 3b.
Signal
N/C
VDD
F0
D15
N/C
D14
D13
GND
D12
GND
VDD
VDD
D11
D10
D9
GND
CLK
CLK
CLK
GND
GND
D8
VDD
D7
D6
D5
D4
GND
D3
N/C
D2
D1
N/C
5
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