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PDSP16256C0 Schematic ( PDF Datasheet ) - Mitel Networks Corporation

Teilenummer PDSP16256C0
Beschreibung Programmable FIR Filter
Hersteller Mitel Networks Corporation
Logo Mitel Networks Corporation Logo 




Gesamt 28 Seiten
PDSP16256C0 Datasheet, Funktion
PDSP16256/A
Programmable FIR Filter
DS3709
Issue 7.1
June 1999
Features
q Sixteen MACs in a Single Device
q Basic Mode is 16-Tap Filter at up to 25MHz
Sample Rates
q Programmable to give up to 128 Taps with
Sampling Rates Proportionally Reducing to
3·125MHz
q 16-bit Data and 32-bit Accumulators
q Can be configured as One Long Filter or Two
Half-Length Filters
q Decimate-by-two Option will Double the Filter
Length
q Coefficients supplied from Host System or local
EPROM
Applications
q High Performance Digital Filters
Ordering Information
Commercial (0°C to 170°C)
PDSP16256A/C0/AC 25MHz, PGA package
Industrial (240°C to 185°C)
PDSP16256 B0/AC 20MHz, PGA package
PDSP16256 B0/GC 20MHz, QFP package
Military (255°C to 1125°C)
PDSP16256 MC/AC1R 20MHz, MIL-STD-883*
(latest revision), PGA package
PDSP16256 MC/GC1R 20MHz, MIL-STD-883*
(latest revision), QFP package
*See notes following Electrical Characteristics for further
information on MIL-STD-883 screening
Associated Products
PDSP16350 I/Q Splitter/NCO
PDSP16510A FFT Processor
Description
The PDSP16256 contains sixteen multiplier -
accumulators, which can be multi cycled to provide
from 16 to 128 stages of digital filtering. Input data
and coefficients are both represented by 16-bit
two’s complement numbers with coefficients
converted internally to 12 bits and the results being
accumulated up to 32 bits.
In 16-tap mode the device samples data at the
system clock rate of up to 25MHz. If a lower sample
rate is acceptable then the number of stages can be
increased in powers of two up to a maximum of 128.
Each time the number of stages is doubled, the
sample clock rate must be halved with respect to the
system clock. With 128 stages the sample clock is
therefore one eighth of the system clock.
In all speed modes devices can be cascaded to
provide filters of any length, only limited by the
possibility of accumulator overflow. The 32-bit
results are passed between cascaded devices
without any intermediate scaling and subsequent
loss of precision.
The device can be configured as either one long
filter or two separate filters with half the number of
taps in each. Both networks can have independent
inputs and outputs.
Both single and cascaded devices can be operated
in decimate-by-two mode. The output rate is then
half the input rate, but twice the number of stages
are possible at a given sample rate. A single device
with a 20MHz clock would then, for example,
provide a 128-stage low pass filter, with a 5MHz
input rate and 2·5MHz output rate.
Coefficients are stored internally and can be down
loaded from a host system or an EPROM. The latter
requires no additional support, and is used in stand
alone applications. A full set of coefficients is then
automatically loaded at power on, or at the request
of the system. A single EPROM can be used to
provide coefficients for up to 16 devices.






PDSP16256C0 Datasheet, Funktion
PDSP16256
SCLK
FRUN
DA15:0
F31:0 OEN
SWAP
A7:0
C15:0
CCS
WEN
CS
BYTE
EPROM
FEN
DFEN
DCLR
RES
COEFFICIENT
STORAGE
AND
CONTROL
NETWORK
A
MUX
DUAL
MODE
NETWORK
B
SINGLE
MODE
CLKOP BUSY
DB15:0
X31:0
Figure. 4 Block Diagram
Operational Overview
The PDSP16256 is an application specific FIR filter for
use in high performance digital signal processing
systems. Sampling rates can be up to 25MHz. The
device provides the filter function without any software
development, and the options are simply selected by
loading a control register. The device can be user
configured as either a single filter, or as two separate
filters. The latter can provide two independent filters for
the in-phase and quadrature channels after IQ splitting,
or can provide two filters in cascade for greater stop
band rejection.
The device operates from a system clock, with rates up
to 25MHz. This clock must be 1, 2, 4, or 8 times the
required sampling frequency, with the higher
multiplication rates producing longer filter networks at
the expense of lower sampling rates. Devices can be
connected in cascade to produce longer filter lengths.
This can be accomplished without the need for any
additional external data delays, and all the single device
options remain available.
Continuous inputs are accepted, and continuous results
produced after the internal pipeline delay. Connection
can be made directly to an A-D converter. The filter
operation can be synchronised to a Filter Enable signal
(FEN) whose positive going edge marks the first data
sample. The internal multiplier accumulator array can be
cleared with a dedicated input. This is necessary if
erroneous results obtained during the normal data ‘flush
6
through’ are not permissible in the system.
Coefficients can be loaded from a host system using a
conventional peripheral interface and separate data
bus. Alternatively, they can be loaded as a complete set
from a byte wide EPROM. The device produces
addresses for the EPROM and a BUSY output indicates
that the transfer is occurring. Up to sixteen devices can
have their coefficients supplied from a single EPROM.
These devices need not necessarily be part of the same
filter network.
Each of the filter networks shown in Fig. 4 contains eight
systolic multiplier accumulator stages; an example with
four stages is shown in Fig. 5. Input data flows through
the delay lines and is presented for multiplication with the
required coefficient. This is added to either the last result
from this accumulator or the result from the previous
accumulator. The filter results progress along the adders
at the data sample rate. If the sample rate equals SCLK
divided by four, for example, then the accumulated result
is passed onto the next stage every fourth cycle. The
structure described is highly efficient when used to
calculate filtered results from continuous input data.
A comprehensive digital filter design program is
available for PC compatible machines. This will optimise
the filter coefficients for the filter type required and
number of taps available at the selected sample rate
within the PDSP16256 device. An EPROM file can be
automatically generated in Motorola S-record format.

6 Page









PDSP16256C0 pdf, datenblatt
PDSP16256
128 TAP
127
NO SWAP
POSSIBLE
0
64 TAP
127
FILTER B
NO SWAP
POSSIBLE
64
63
FILTER A
NO SWAP
POSSIBLE
0
12
RESULTS
OUT
FEN
DB15:0 FEN F31:0
INTERFACE
DEVICE
DA15:0 DFEN X31:0
DB15:0 FEN F31:0
INTERMEDIATE
DEVICE
DA15:0 DFEN X31:0
DB15:0 FEN F31:0
TERMINATION
DEVICE
DA15:0 DFEN X31:0
DATA IN
Figure. 13 Full speed cascaded system
64 TAP
127
32 TAP
127
16 TAP
127
UPPER
BANK
NOT USED
64 64
63 63
NOT USED
LOWER
BANK
UPPER
BANK
32
31
LOWER
BANK
00
(a) Single Filters
32 TAP
16 TAP
127 127
32
31 UPPER
16 BANK
15 LOWER
0 BANK
8 TAP
127
B UPPER
BANK
96
95
NOT USED
A UPPER
BANK
64
63
B LOWER
BANK
32
31
A LOWER
BANK
64
63
B UPPER
48
47
A UPPER
32
31
B LOWER
16
15
A LOWER
00
(b) Dual Filters
NOT USED
32
31 B UPPER
A UPPER
B LOWER
0 A LOWER
Figure. 14 Coefficient memory map

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