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PDSP16116 Schematic ( PDF Datasheet ) - Mitel Networks Corporation

Teilenummer PDSP16116
Beschreibung 16 X 16 Bit Complex Multiplier
Hersteller Mitel Networks Corporation
Logo Mitel Networks Corporation Logo 




Gesamt 17 Seiten
PDSP16116 Datasheet, Funktion
Supersedes October 1996 version, DS3707 - 4.2
PDSP16116
16 X 16 Bit Complex Multiplier
DS3707 - 5.3 October 1997
The PDSP16116 contains four 16316 array multipliers, two
32-bit adder/subtractors and all the control logic required to sup-
port Block Floating Point Arithmetic as used in FFT applications.
The PDSP16116A variant will multiply two complex (16116)
bit words every 50ns and can be configured to output the com-
plete complex (32132) bit result within a single cycle. The data
format is fractional two’s complement.
In combination with a PDSP16318A, the PDSP16116A forms
a two-chip 20MHz complex multiplier accumulator with 20-bit
accumulator registers and output shifters. The PDSP16116A in
combination with two PDSP16318As and two PDSP1601As
forms a complete 20MHz Radix 2 DIT FFT butterfly solution
which fully supports block floating point arithmetic. The
PDSP16116 has an extremely high throughput that is suited to
recursive algorithms as all calculations are performed with a
single pipeline delay (two cycle fall-through).
FEATURES
I Complex Number (16116)3(16116) Multiplication
I Full 32-bit Result
I 20MHz Clock Rate
I Block Floating Point FFT Butterfly Support
I (21)3(21) Trap
I Two’s Complement Fractional Arithmetic
I TTL Compatible I/O
I Complex Conjugation
I 2 Cycle Fall Through
I 144-pin PGA or QFP packages
APPLICATIONS
I Fast Fourier Transforms
I Digital Filtering
I Radar and Sonar Processing
I Instrumentation
I Image Processing
ORDERING INFORMATION
PDSP16116 MC GGDR 10MHz MIL-883 screened
PDSP16116A B0 AC 20MHz Industrial
PDSP16116A A0 AC 20MHz Military
PDSP16116A B0 GG 20MHz Industrial
PDSP16116A MC GGDR 20MHz MIL-883 screened
PDSP16116B B0 AC 25MHz Industrial
PDSP16116D B0 GG 31·5MHz Industrial
XR15:0
XI15:0
YR15:0
YI15:0
REG REG REG REG
MULT
MULT
MULT
MULT
REG REG REG REG
ADD/SUB
ADD/SUB
SHIFT
SHIFT
REG REG
PR15:0
PI15:0
Fig. 1 Simplified block diagram
ASSOCIATED PRODUCTS
PDSP16318/A Complex Accumulator
PDSP16112/A (16116)3(12112) Complex Multiplier
PDSP16330/A Pythagoras Processor
PDSP1601/A ALU and Barrel Shifter
PDSP16350 Precision Digital Modulator
PDSP16256 Programmable FIR Filter
PDSP16510 Single Chip FFT Processor






PDSP16116 Datasheet, Funktion
PDSP16116
NORMAL MODE OPERATION
When the MBFP mode select input is held low the ‘Normal’
mode of operation is selected. This mode supports all complex
multiply operations that do not require block floating point
arithmetic.
Complex two’s complement fractional data is loaded into the
X and Y input registers via the X and Y Ports on the rising edge
of CLK. The X and Y port registers are individually enabled by
the CEX and CEY signals respectively. If the registers are re-
quired to be permanently enabled, then these signals may be
tied to ground.
The Real and Imaginary components of the fractional data
are each assumed to have the following format:
Bit Number
Weighting
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S 21 22 23 24 25 26 27 28 29 210 211 212 213 214 215
Where S = sign bit, which has an effective weighting of 220
The value of the 16-bit two’s complement word is (213S)1(bit143221)1(bit133222)1(bit123223) …
Multiplier Stage
On each clock cycle the contents of the input registers are passed
to the four multipliers to start a new complex multiply operation.
Each complex multiply operation requires four partial products
(XR3YR), (XR3YI), (XI3YR), (XI3YI), all of which are calculated
in parallel by the four 16316 multipliers. Only one clock cycle is
required to complete the multiply stage before the multiplier results
are loaded into the multiplier output registers for passing on to the
adder/ subtractors in the next cycle. Each multiplier produces a 31-
bit result with the duplicate sign bit eliminated. The format of the
output data from the multipliers is:
Bit Number 30 29 28 27 26 25 24
Weighting
S 21 22 23 24 25 26
The effective weighting of the sign bit is 220
76543210
223 224 225 226 227 228 229 230
Adder/Subtractor Stage
The 31-bit real and imaginary results from the multipliers
are passed to two 32-bit adder/subtractors. The adder calcu-
lates the imaginary result [(XR 3 YI) 1 (XI 3 YR)] and the
subtractor calculates the real result (XR 3 YR) = (XI 3 YI).
Each adder/subtractor produces a 32-bit result with the
following format:
Bit Number 31 30 29 28 27 26
Weighting
S 20 21 22 23 24
The effective weighting of the sign bit is 221
Rounding
The ROUND control when asserted rounds the most
significant 16 bits of the full 32-bit result from the shifter. If the
ROUND signal is active (high), then bit 16 is set to ‘1’, rounding
the most significant 16 bits of the shifted result. (The least
876543210
222 223 224 225 226 227 228 229 230
significant 16 bits are unaffected). Inserting a ‘1’ ensures that
the rounding error is never greater than 1 LSB and that no DC
bias is introduced as a result of the rounding processes. The
format of the rounded result is:
Bit Number
Weighting
31 30 29 28 27
S 20 21 22 23
18 17 16 15 14 13
212 213 214 215 216 217
210
228 229 230
ROUNDED VALUE
The effective weighting of the sign bit is 221
Result Correction
Due to the nature of the fraction two’s complement repre-
sentation it is possible to represent 21 exactly but not 11. With
conventional multipliers this causes a problem when 21 is mul-
tiplied by 21 as the multiplier produces an incorrect result. The
PDSP16116 includes a trap to ensure that the most positive
number (value = 1·2230, hex = 7FFFFFFFF) is substituted for
the incorrect result. The multiplier result is therefore always a
correct fractional value. Fig.2 shows the value ‘1’ being multi-
plexed into the data path controlled by four comparators.
LSBs
Complex Conjugation
Either the X or Y input data may be complex conjugated by
asserting the CONX or CONY signals respectively. Asserting
either of these signals has the effect of inverting (multiplying
by 21 ) the imaginary component of the respective input. Table 3
shows the effect of CONX and CONY on the X and Y inputs.
CONX
Low
High
Low
High
CONY Function
Operation
Low
Low
High
High
X3Y
Conj. X 3 Y
X 3 Conj. Y
Invalid
(XR 1 XI)3(YR 1 YI)
(XR 2 XI)3(YR 1 YI)
(XR 1 XI)3(YR 2 YI)
Invalid
Table 3 Conjugate functions
6

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PDSP16116 pdf, datenblatt
PDSP16116
CLK
OUTPUT P PORTS
OUTPUT SFTA1:0
INPUT DATA X AND Y
INPUT CONTROLS CEX AND CEY
INPUT CONTROLS CONX AND CONY
INPUT CONTROL WTB1:0
tCP
VALID DATA
tCSFTA
tCLK
tCLKH
tCLKL
VALID DATA
tCSFTA
tDS
tCES
tCONS
tWS
tDH
tCEH
tCONH
tWH
Fig. 9 Normal mode timing
OER AND OEI
OUTPUT P PORTS
tOPLZ
HIGH Z
tOPZL
HIGH Z
Fig. 10 Output tristate timing
tOPZH
tOPHZ
HIGH Z
Test
Delay from
output high
to output
high Z (tOPHZ)
Delay from
output low
to output
high Z (tOPLZ)
Delay from
output high Z
to output low
(tOPZL)
Delay from
output high Z
to output high
(tOPZH)
Waveform measurement level
VH 0·5V
VT = 0V
VT = VDD
0·5V
VL
1·5V
0·5V
1·5V
0·5V
VH is the voltage reached when the output is driven high
VL is the voltage reached when the output is driven low
1·5k
VT
DUT
30p
Three state delay measurement load
Fig. 11 Three state delay measurement
12

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