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PDIUSBH11ANB Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PDIUSBH11ANB
Beschreibung Universal Serial Bus Hub
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 28 Seiten
PDIUSBH11ANB Datasheet, Funktion
INTEGRATED CIRCUITS
PDIUSBH11A
Universal Serial Bus Hub
Product specification
Supersedes data of 1998 Jun 04
Philips
Semiconductors
1999 Jul 22






PDIUSBH11ANB Datasheet, Funktion
Philips Semiconductors
Universal Serial Bus Hub
Product specification
PDIUSBH11A
PIN DESCRIPTION
The PDIUSBH11A has two modes of operation. The first mode (Mode 0) configures the pins DNx_GL_N for GoodLinkLED indication. The
second mode (Mode 1) configures the LED pins as per port overcurrent condition pins. An overcurrent condition on any port can be uniquely
identified in Mode 1. However, all downstream ports are disabled as a result of a single overcurrent condition. In addition to the two modes of
operation, the PDIUSBH11A can also be configured to take either a 48 MHz crystal oscillator (for backward compatibility to PDIUSBH11) or a 12
MHz crystal.
The internal 4X clock multiplier PLL will be activated when 12 MHz input XTAL mode is selected. Also, the output clock frequency is now
programmable rather than fixed to 12 MHz. The output clock frequency can be programmed through the Set Mode command. All these new
features are added while maintaining backward compatibility to the PDIUSBH11 through TEST2 and TEST1 pins.
TEST2 TEST1
MODE
00
MODE 0
(GoodLink)
01
MODE 0
(GoodLink)
10
MODE 1
(Individual Overcurrent)
11
MODE 1
(Individual Overcurrent)
NOTE:
1. Pin TEST3 should always be connected to Ground at all times.
INPUT XTAL FREQUENCY
(MHz)
48
OUTPUT CLOCK FREQUENCY
(AT RESET)
12MHz
12 4 MHz
12 4 MHz
48 12 MHz
Pin configuration
TEST1 1
32 UP_DM
TEST2 2
31 UP_DP
TEST3 3
RESET_N 4
30 AVCC
29 AGND
GND 5
28 DN2_DM
XTAL1 6
27 DN2_DP
XTAL2 7
26 DN3_DM
CLKOUT 8
VCC 9
OCURRENT_N / OCURRENT2_N * 10
DUAL
IN-LINE
PACKAGE
25 DN3_DP
24 DN4_DM
23 DN4_DP
SWITCH_N 11
22 DN5_DM
SUSPEND 12
21 DN5_DP
DN2_GL_N 13
20 GND
DN3_GL_N / OCURRENT3_N * 14
19 SCL
DN4_GL_N / OCURRENT4_N * 15
18 SDA
DN5_GL_N / OCURRENT5_N * 16
17 INT_N
SV01047
NOTE:
Pins 10, 14, 15, and 16 show alternative pin functions, depending on mode of operation (Mode 0 or Mode 1) as described in Pin Description.
1999 Jul 22
6

6 Page









PDIUSBH11ANB pdf, datenblatt
Philips Semiconductors
Universal Serial Bus Hub
Product specification
PDIUSBH11A
Set Mode
Command
Data
: F3h
: Write 2 bytes
The Set Mode command is followed by two data writes. The first
byte contains the configuration byte values. The second byte is the
clock division factor byte.
Configuration Byte
76 54 32 1 0
10 00 11 01
POWER ON VALUE
REMOTE WAKEUP
NO LAZYCLOCK
CLOCK RUNNING
DEBUG MODE
SoftConnect
CONNECT DOWNSTREAM RESISTORS
NON-BLINKING LEDs
EMBEDDED FUNCTION MODE
SV00842
Remote Wakeup
No LazyClock
Clock Running
Debug Mode
SoftConnect
A ‘1’ indicates that a remote wakeup feature
is ON. Bus reset will set this bit to ‘1’.
A ‘1’ indicates that CLKOUT will not switch
to LazyClock. A ‘0’ indicates that the
CLKOUT switches to LazyClock 1ms after
the Suspend pin goes high. LazyClock
frequency is 30 kHz (± 40%). The
programmed value will not be changed by a
bus reset.
A ‘1’ indicates that the internal clocks and
PLL are always running even during
Suspend state. A ‘0’ indicates that the
internal clock, crystal oscillator and PLL are
stopped whenever not needed. To meet the
strict Suspend current requirement, this bit
needs to be set to ‘0’. The programmed
value will not be changed by a bus reset.
A ‘1’ indicates that all errors and “NAKing”
are reported and a ‘0’ indicates that only OK
and babbling are reported. The programmed
value will not be changed by a bus reset.
A ‘1’ indicates that the upstream pull-up
resistor will be connected if VBUS is
available. A ‘0’ means that the upstream
resistor will not be connected. The
programmed value will not be changed by a
bus reset.
Connect Downstream
Resistors
A ‘1’ indicates that downstream resistors are
connected. A ‘0’ means that downstream
resistors are not connected. The
programmed value will not be changed by a
bus reset.
Non-blinking LEDs
A ‘1’ indicates that GoodLinkLEDs will
NOT blink when there is traffic. Leave this bit
at ‘0’ to achieve blinking LEDs. The
programmed value will not be changed by a
bus reset.
Embedded Function
Mode
A ‘1’ indicates single embedded function
mode. A ‘0’ indicates multiple (3) embedded
function mode. See endpoint descriptions for
details. The programmed value will not be
changed by a bus reset.
Clock Division Factor Byte
76 54 32 1 0
XX 0 0 0 0 1 1
XX 1 1 1 0 1 1
POWER ON VALUE FOR 48MHz INPUT
POWER ON VALUE FOR 12MHz INPUT
CLOCK DIVISION FACTOR
RESERVED
SV00843
Clock Division Factor
The value indicates clock division factor for
CLKOUT. The output frequency is
48 MHz/(N+1) where N is the Clock Division
Factor. When the 48MHz input crystal
frequency is selected, the reset value is 3.
This will give a default output frequency at
CLKOUT pin of 12 MHz, thus maintaining
backward compatibility to the PDIUSBH11.
When the 12 MHz input crystal frequency is
selected, the reset value is 11. This will
produce the lowest output frequency of 4
MHz which can then be programmed up by
the user. The PDIUSBH11A design ensures
no glitching during frequency change. The
programmed value will not be changed by a
bus reset.
1999 Jul 22
12

12 Page





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