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PDI1394P22BD Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PDI1394P22BD
Beschreibung 3-port physical layer interface
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PDI1394P22BD Datasheet, Funktion
INTEGRATED CIRCUITS
PDI1394P22
3-port physical layer interface
Objective specification
1999 Jul 09
Philips
Semiconductors






PDI1394P22BD Datasheet, Funktion
Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P22
6.0 BLOCK DIAGRAM
CPS
LPS
/ISO
C/LKON
SYSCLK
LREQ
CTL0
CTL1
D0
D1
D2
D3
D4
D5
D6
D7
PC0
PC1
PC2
CNA
LINK
INTERFACE
I/O
R0
R1
TPBIAS0
TPBIAS1
TPBIAS2
PD
/RESET
RECEIVED DATA
DECODER/
RETIMER
ARBITRATION
AND CONTROL
STATE MACHINE
LOGIC
BIAS VOLTAGE
AND
CURRENT
GENERATOR
TRANSMIT
DATA
ENCODER
CABLE POWER
DETECTOR
CPS
CABLE PORT 0
TPA0+
TPA0–
TPB0+
TPB0–
CABLE PORT 1
CABLE PORT 2
CRYSTAL
OSCILLATOR,
PLL SYSTEM,
AND CLOCK
GENERATOR
TPA1+
TPA1–
TPB1+
TPB1–
TPA2+
TPA2–
TPB2+
TPB2–
XI
XO
SV01743
7.0 FUNCTIONAL SPECIFICATION
The PDI1394P22 requires only an external 24.576 MHz crystal as a
reference. An external clock can be provided instead of a crystal. An
internal oscillator drives an internal phase-locked loop (PLL), which
generates the required 393.216 MHz reference signal. This
reference signal is internally divided to provide the clock signals
used to control transmission of the outbound encoded Strobe and
Data information. A 49.152 MHz clock signal, supplied to the
associated LLC for synchronization of the two chips, is used for
resynchronization of the received data. The Power Down (PD)
function, when enabled by asserting the PD terminal high, stops
operation of the PLL and disables all circuits except the cable bias
detectors at the TPB terminals. The port transmitter circuitry and the
receiver circuitry are also disabled when the port is disabled,
suspended, or disconnected.
The PDI1394P22 supports an optional isolation barrier between
itself and its LLC. When the /ISO input terminal is tied high, the
LLC interface outputs behave normally. When the /ISO terminal is
tied low, internal differentiating logic is enabled, and the outputs are
driven such that they can be coupled through a capacitive or
transformer galvanic isolation barrier as described in IEEE 1394a
section 5.9.4. To operate with single capacitor (bus holder) isolation,
the /ISO on the PHY terminal must be tied high.
Data bits to be transmitted through the cable ports are received from
the LLC on two, four or eight parallel paths (depending on the
requested transmission speed). They are latched internally in the
PDI1394P22 in synchronization with the 49.152 MHz system clock.
These bits are combined serially, encoded, and transmitted at
98.304/196.608/392.216 Mbits/s (referred to as S100, S200, and
S400 speed, respectively) as the outbound data-strobe information
stream. During transmission, the encoded data information is
transmitted differentially on the TPB cable pair(s), and the encoded
strobe information is transmitted differentially on the TPA cable
pair(s).
During packet reception the TPA and TPB transmitters of the
receiving cable port are disabled, and the receivers for that port are
enabled. The encoded data information is received on the TPA cable
pair, and the encoded strobe information is received on the TPB
cable pair. The received data-strobe information is decoded to
recover the receive clock signal and the serial data bits. The serial
1999 Jul 09
6

6 Page









PDI1394P22BD pdf, datenblatt
Philips Semiconductors
3-port physical layer interface
Objective specification
PDI1394P22
16.0 INTERNAL REGISTER CONFIGURATION
There are 16 accessible internal registers in the PDI1394P22. The
configuration of the registers at addresses 0 through 7 (the base
registers) is fixed, while the configuration of the registers at
addresses 8h through Fh (the paged registers) is dependent upon
which one of eight pages, numbered 0h through 7h, is currently
selected. The selected page is set in base register 7h.
The configuration of the base registers is shown in Table 1, and
corresponding field descriptions are given in Table 2. The base
register field definitions are unaffected by the selected page number.
A reserved register or register field (marked as Reserved or Rsvd in
the following register configuration tables) is read as 0, but is subject
to future usage. All registers in address pages 2 through 6 are
reserved.
Table 1. Base Register Configuration
ADDRESS
0000
0001
0010
0011
0100
0101
0110
0111
01
RHB
L
RPIE
IBR
Extended (111b)
PHY_Speed (010b)
C
ISBR
Page_Select
BIT POSITION
23456
Physical ID
R
Gap_Count
Rsvd
Num_Ports (0011b)
Rsvd
Delay (0000b)
Jitter (000)
Pwr_Class
CTOI
CPSI
STOI
PEI
EAA
Reserved
Rsvd
Port Select
7
CPS
EMC
Table 2. Base Register Field Descriptions
FIELD
SIZE TYPE
DESCRIPTION
Physical ID
6 Rd This field contains the physical address ID of this node determined during self–ID. The physical-ID is
invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status
transfer.
R 1 Rd Root. This bit indicates that this node is the root node. The R bit is reset to 0 by bus reset, and is set to
1 during tree-ID if this node becomes root.
CPS
1 Rd Cable-power-status. This bit indicates the state of the CPS input terminal. The CPS terminal is normally
tied to serial bus cable power through a 370 k–410 kresistor. A 0 in this bit indicates that the cable
power voltage has dropped below its threshold for ensured reliable operation.
RHB
1 Rd/Wr Root-holdoff bit. This bit instructs the PHY to attempt to become root after the next bus reset. The RHB
bit is reset to 0 by a hardware reset, and is unaffected by a bus reset.
IBR 1 Rd/Wr Initiate bus reset. This bit instructs the PHY to initiate a long (166 µs) bus reset at the next opportunity.
Any receive or transmit operation in progress when this bit is set will complete before the bus reset is
initiated. The IBR bit is reset to 0 after a hardware reset or a bus reset.
Gap_Count
6 Rd/Wr Arbitration gap count. This value is used to set the subaction (fair) gap, arb-reset gap, and arb-delay
times. The gap count can be set either by a write to the register, or by reception or transmission of a
PHY_CONFIG packet. The gap count is reset to 3Fh by hardware reset or after two consecutive bus
resets without an intervening write to the gap count register (either by a write to the PHY register or by
a PHY_CONFIG packet).
Extended
3 Rd Extended register definition. For the PDI1394P22, this field is 111b, indicating that the extended register
set is implemented.
Num_Ports
4 Rd Number of ports. This field indicates the number of ports implemented in the PHY. For the PDI1394P22
this field is 3.
PHY_Speed 3 Rd PHY speed capability. For the PDI1394P22, this field is 010b, indicating S400 speed capability.
Delay
4 Rd PHY repeater data delay. This field indicates the worst case repeater data delay for this PHY,
expressed as 144+(delay × 20) ns. For the PDI1393P21, this field is 0.
L 1 Rd/Wr Link active status. This bit indicates that this node’s link is active. The logical AND of this bit and the
LPS active status is replicated in the L field (bit 9) of the self-ID packet. This bit is set to 1 by a
hardware reset and is unaffected by a bus reset.
C 1 Rd/Wr Contender status. This bit indicates that this node is a contender for the bus or isochronous resource
manager. This bit is replicated in the “c” field (bit 20) of the self-ID packet. This bit is set to the state
specified by the C/LKON input terminal by a hardware reset and is unaffected by a bus reset.
Jitter
3 Rd
PHY repeater jitter. This field indicates the worst case difference between the fastest and slowest
repeater data delay, expressed as (Jitter + 1) × 20 ns. For the PDI1394P22, this field is 0.
1999 Jul 09
12

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