PDF PDI1394P21BE Data sheet ( Hoja de datos )

Número de pieza	PDI1394P21BE
Descripción	3-port physical layer interface
Fabricantes	NXP Semiconductors
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No Preview Available ! INTEGRATED CIRCUITS PDI1394P21 3-port physical layer interface Objective specification 1999 Jul 09 Philips Semiconductors 1 page Philips Semiconductors 3-port physical layer interface Objective specification PDI1394P21 Name /RESET Pin Type CMOS 5V tol Pin Numbers 78 R0, R1 Bias 66, 67 SYSCLK TEST0 TEST1 TPA0+, TPA1+, TPA2+ TPA0–, TPA1–, TPA2– TPB0+, TPB1+, TPB2+ TPB0–, TPB1–, TPB2– TPBIAS0, TPBIAS1, TPBIAS2 CMOS CMOS CMOS Cable Cable Cable Cable Cable 2 33 32 45, 52, 58 44, 51, 57 43, 50, 56 42, 49, 55 46, 53, 59 XO, XI Crystal 77, 76 I/O Description I Logic reset input. Asserting this terminal low resets the internal logic. An internal pull-up resistor to VDD is provided so only an external delay capacitor in parallel with a resistor is required for proper power-up operation. For more information, refer to Section 17.3. This input is otherwise a standard logic input, and can also be driven by an open-drain type driver. — Current setting resistor terminals. These terminals are connected to an external resistance to set the internal operating currents and cable driver output currents. A resistance of 6.34 kΩ ±1% is required to meet the IEEE Std 1394–1995 output voltage limits. O System clock output. Provides a 49.152 MHz clock signal, synchronized with data transfers, to the LLC. I Test control input. This input is used in manufacturing tests of the PDI1394P21. For normal use, this terminal should be tied to GND. I Test control input. This input is used in manufacturing tests of the PDI1394P21. For normal use, this terminal should be tied to GND. I/O Twisted-pair cable A differential signal terminals. Board traces from each pair of positive and negative differential signal terminals should be kept I/O matched and as short as possible to the external load resistors and to the cable connector. I/O Twisted-pair cable B differential signal terminals. Board traces from each pair of positive and negative differential signal terminals should be kept I/O matched and as short as possible to the external load resistors and to the cable connector. I/O Twisted-pair bias output. This provides the 1.86V nominal bias voltage needed for proper operation of the twisted-pair cable drivers and receivers, and for signaling to the remote nodes that there is an active cable connection. Each of these terminals must be decoupled with a 0.3 µF–1 µF capacitor to ground. — Crystal oscillator inputs. These terminals connect to a 24.576 MHz parallel resonant fundamental mode crystal. The optimum values for the external shunt capacitors are dependent on the specifications of the crystal used. Can also be driven by an external clock generator (leave XO unconnected in this case). 1999 Jul 09 5 5 Page Philips Semiconductors 3-port physical layer interface Objective specification PDI1394P21 13.0 THERMAL CHARACTERISTICS SYMBOL PARAMETER TEST CONDITION RΘjA Junction-to-free-air thermal resistance Board mounted, no air flow LIMITS UNIT MIN TYP MAX TBD °C/W 14.0 AC CHARACTERISTICS SYMBOL PARAMETER Transmit jitter Transmit skew tr TPA, TPB differential output voltage rise time tf TPA, TPB differential output voltage fall time tSU Setup time, CTL0, CTL1, D1–D7, LREQ to SYSCLK tH Hold time, CTL0, CTL1, D1–D7, LREQ after SYSCLK tD Delay time SYSCLK to CTL0, CTL1, D1–D7 CONDITION TPA, TPB Between TPA and TPB 10% to 90%; At 1394 connector 90% to 10%; At 1394 connector 50% to 50%; See Figure 2 50% to 50%; See Figure 2 50% to 50%; See Figure 3 MIN TYP MAX UNIT 0.15 ns 0.10 ns 0.5 1.2 ns 0.5 1.2 ns 5 ns 0 ns 0.5 11 ns 15.0 TIMING WAVEFORMS TPAn+ TPBn+ 56 Ω TPAn– TPBn– SV01098 Figure 1. Test load diagram SYSCLK Dn, CTLn, LREQ tD SV01100 Figure 3. Dn, CTLn, output delay relative to SYSCLK SYSCLK Dn, CTLn, LREQ tSU tH SV01099 Figure 2. Dn, CTLn, LREQ input setup and hold times 1999 Jul 09 11 11 Page

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