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PDI1394P11ABD Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PDI1394P11ABD
Beschreibung 3-port physical layer interface
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 20 Seiten
PDI1394P11ABD Datasheet, Funktion
INTEGRATED CIRCUITS
PDI1394P11A
3-port physical layer interface
Preliminary specification
1999 Mar 10
Philips
Semiconductors






PDI1394P11ABD Datasheet, Funktion
Philips Semiconductors
3-port physical layer interface
Preliminary specification
PDI1394P11A
9.0 ABSOLUTE MAXIMUM RATINGS1, 2
In accordance with the Absolute Maximum Rating System (IEC 134). Voltages are referenced to GND (ground = 0V).
SYMBOL
PARAMETER
CONDITION
LIMITS
MIN MAX
UNIT
VDD DC supply voltage
–0.3 4.6 V
VI DC input voltage3
Inputs CPS, TPAn, TPBn, FILTER, XI
–0.5
VDD+0.5
V
VI,5t DC input voltage
5V tolerant digital inputs RESET–, LPS, LREQ, PD,
CTL[0:1], D[0:3], TESTM[2:1], C/LKON, PC[0:2], ISO–
–0.5
5.5 V
VO DC output voltage3
–0.5
VDD+0.5
V
IIK DC input diode current
VI < 0
– –50 mA
IOK DC output diode current
VO < 0 or VO > VDD
±50 mA
Tstg Storage temperature range
–65
+150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output clamp current ratings are observed.
10.0 CABLE DRIVER
SYMBOL
PARAMETER
TEST CONDITION
LIMITS
UNIT
MIN TYP MAX
VOD
IO(diff)
Differential output voltage
Difference current, TPA+, TPA–, TPB+, TPB–
56 W load
172
Driver enabled, speed signaling OFF –1.051
265
1.051
mV
mA
ISP Common mode speed signaling current, TPB+, TPB– 200Mbit speed signaling enabled
+2.532
+4.842 mA
VOFF OFF state common mode voltage
Drivers disabled
20 mV
NOTES:
1. Limits defined as algebraic sum of TPA+ and TPA– driver currents. Limits also apply to TPB+ and TPB– algebraic sum of driver currents.
2. Limits defined as one half of the algebraic sum of currents flowing into TPB+ and TPB–.
11.0 CABLE RECEIVER
SYMBOL
PARAMETER
IIC Common mode input current
ZID Differential input impedance
ZIC Common mode input impedance
VTH Receiver input threshold voltage
VTH Cable bias detect threshold, TPBn cable inputs
TEST CONDITION
Driver disabled
Driver disabled
Driver disabled
Driver disabled
LIMITS
MIN TYP MAX
–20 20
15
6
20
24
–60 60
0.6 1.0
UNIT
µA
k
pF
k
pF
mV
V
1999 Mar 10
6

6 Page









PDI1394P11ABD pdf, datenblatt
Philips Semiconductors
3-port physical layer interface
Preliminary specification
PDI1394P11A
17.3 Bushold and Link/PHY single capacitor
galvanic isolation
17.3.1 Bushold
The PDI1394P11A uses an internal bushold circuit on each of the
indicated pins to keep these CMOS inputs from “floating” while being
driven by a 3-Stated device or input coupling capacitor.
Unterminated high impedance inputs react to ambient electrical
noise which cause internal oscillation and excess power supply
current draw.
The following pins have bushold circuitry enabled when the ISO– pin
is in the logic “1” state:
Pin No.
2
3
7
11
12
13
14
15
16
Name
LPS
LREQ
PD
CTL0
CTL1
D0
D1
D2
D3
Function
Link power status line
Link request line
Power down pin
Phy/Link Interface bi-directional control line 0
Phy/Link Interface bi-directional control line 1
Phy/Link Interface bi-directional data line 0
Phy/Link Interface bi-directional data line 1
Phy/Link Interface bi-directional data line 2
Phy/Link Interface bi-directional data line 3
Philips bushold circuitry is designed to provide a high resistance
pull-up or pull-down on the input pin. This high resistance is easily
overcome by the driving device when its state is switched. Figure 6
shows a typical bushold circuit applied to a CMOS input stage. Two
weak MOS transistors are connected to the input. An inverter is also
connected to the input pin and supplies gate drive to both
transistors. When the input is LOW, the inverter output drives the
lower MOS transistor and turns it on. This re-enforces the LOW on
the input pin. If the logic device which normally drives the input pin
were to be 3-Stated, the input pin would remain “pulled-down” by the
weak MOS transistor. If the driving logic device drives the input pin
HIGH, the inverter will turn the upper MOS transistor on,
re-enforcing the HIGH on the input pin. If the driving logic device is
then 3-Stated, the upper MOS transistor will weakly hold the input
pin HIGH.
The PHY’s outputs can be 3-Stated and single capacitor isolation
can be used with the Link; both situations will allow the Link inputs to
float. With bushold circuitry enabled, these pins are provided with dc
paths to ground, and power by means of the bushold transistors;
this arrangement keeps the inputs in known logical states.
INPUT PIN
INTERNAL
CIRCUITS
Figure 6. Bushold circuit
SV00911
17.3.2 Single capacitor isolation
The circuit example (Figure 7) shows the connections required to
implement basic single capacitor Link/PHY isolation.
The RESET, C/LKON, PD, and LPS pins need special consideration
to implement an isolation scheme. Details can be found in the
Philips Isolation Application Note AN2452.
NOTE: The isolation enablement pins on both devices are in their
“1” states, activating the bushold circuits on each part. The bushold
circuits provide local dc ground references to each side of the
isolating/coupling capacitors. Also note that ground
isolation/signal-coupling must be provided in the form of a parallel
combination of resistance and capacitance as indicated in
IEEE 1394–1995.
APPLICATION
+3.3V
ISOLATED
+3.3V
LINK
PDI1394Lxx
ISO_N
PHY D0
PHY D1
PHY D2
PHY D3
PHYCTL0
PHYCTL1
LREQ
SCLK
APPLICATION GROUND
Cc
Cc
Cc
Cc
Cc
1MEG
Cr
62
13
Cc 14
15
16
Cc 11
12
3
Cc 9
ISO–
D0
D1 PHY
D2 PDI1394P11A
D3
PHYCTL0
PHYCTL1
LREQ
SYSCLK
ISOLATED PHY GROUND
Cc = 0.001µF; Cr = 0.1µF
Figure 7. Single capacitor Link/PHY isolation
SV01048
1999 Mar 10
12

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