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PD45128841G5-A75L-9JF Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer PD45128841G5-A75L-9JF
Beschreibung 128M-bit Synchronous DRAM 4-bank/ LVTTL
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 30 Seiten
PD45128841G5-A75L-9JF Datasheet, Funktion
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD45128441, 45128841, 45128163
128M-bit Synchronous DRAM
4-bank, LVTTL
Description
The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access
memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively.
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
Pulsed interface
Possible to assert random column address in every cycle
Quad internal banks controlled by BA0(A13) and BA1(A12)
Byte control (×16) by LDQM and UDQM
Programmable Wrap sequence (Sequential / Interleave)
Programmable burst length (1, 2, 4, 8 and full page)
Programmable /CAS latency (2 and 3)
Automatic precharge and controlled precharge
CBR (Auto) refresh and self refresh
• ×4, ×8, ×16 organization
Single 3.3 V ± 0.3 V power supply
LVTTL compatible inputs and outputs
4,096 refresh cycles / 64 ms
Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0031N30 (Ver. 3.0)
Date Published August 2001 CP (K)
Printed in Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.






PD45128841G5-A75L-9JF Datasheet, Funktion
µPD45128441, 45128841, 45128163
[µPD45128163]
54-pin Plastic TSOP (II) (10.16mm (400))
2M words × 16 bits × 4 banks
VCC
DQ0
VCCQ
DQ1
DQ2
VSSQ
DQ3
DQ4
VCCQ
DQ5
DQ6
VSSQ
DQ7
VCC
LDQM
/WE
/CAS
/RAS
/CS
BA0(A13)
BA1(A12)
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 Vss
53 DQ15
52 VssQ
51 DQ14
50 DQ13
49 VccQ
48 DQ12
47 DQ11
46 VssQ
45 DQ10
44 DQ9
43 VccQ
42 DQ8
41 Vss
40 NC
39 UDQM
38 CLK
37 CKE
36 NC
35 A11
34 A9
33 A8
32 A7
31 A6
30 A5
29 A4
28 Vss
A0 to A11 Note
: Address inputs
BA0(A13), BA1(A12): Bank select
DQ0 to DQ15
: Data inputs / outputs
CLK : Clock input
CKE
: Clock enable
/CS : Chip select
/RAS
: Row address strobe
/CAS
: Column address strobe
/WE : Write enable
LDQM
: Lower DQ mask enable
UDQM
: Upper DQ mask enable
VCC : Supply voltage
VSS : Ground
VCCQ
: Supply voltage for DQ
VSSQ
: Ground for DQ
NC : No connection
Note A0 to A11 : Row address inputs
A0 to A8 : Column address inputs
6 Data Sheet E0031N30

6 Page









PD45128841G5-A75L-9JF pdf, datenblatt
µPD45128441, 45128841, 45128163
Write command
Fig.4 Column address and write command
(/CS, /CAS, /WE = Low, /RAS = High)
If the mode register is in the burst write mode, this command sets the
burst start address given by the column address to begin the burst
write operation. The first write data in burst mode can input with this
command with subsequent data on following clocks.
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
H
Col.
Read command
Fig.5 Column address and read command
(/CS, /CAS = Low, /RAS, /WE = High)
Read data is available after /CAS latency requirements have been
met. This command sets the burst start address given by the column
address.
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
H
Col.
CBR (auto) refresh command
(/CS, /RAS, /CAS = Low, /WE, CKE = High)
This command is a request to begin the CBR (auto) refresh
operation. The refresh address is generated internally.
Before executing CBR (auto) refresh, all banks must be precharged.
After this cycle, all banks will be in the idle (precharged) state and
ready for a row activate command.
During tRC period (from refresh command to refresh or activate
command), the µPD45128xxx cannot accept any other command.
Fig.6 CBR (auto) refresh command
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
H
12 Data Sheet E0031N30

12 Page





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