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PDF PD45128163-SU Data sheet ( Hoja de datos )
| Número de pieza | PD45128163-SU | |
| Descripción | 128M-bit Synchronous DRAM 4-bank/ LVTTL WTR (Wide Temperature Range) | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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PRELIMINARY DATA SHEET
MOS INTEGRATED CIRCUIT
µPD45128163-SU
128M-bit Synchronous DRAM
4-bank, LVTTL
WTR (Wide Temperature Range)
Description
The µPD45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as
2,097,152 × 16 × 4 (word × bit × bank).
The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.
All inputs and outputs are synchronized with the positive edge of the clock.
The synchronous DRAMs are compatible with Low Voltage TTL (LVTTL).
These products are packaged in 54-pin TSOP (II).
Features
• Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
• Pulsed interface
• Possible to assert random column address in every cycle
• Quad internal banks controlled by BA0(A13) and BA1(A12)
• Byte control by LDQM and UDQM
• Programmable Wrap sequence (Sequential / Interleave)
• Programmable burst length (1, 2, 4, 8 and full page)
• Programmable /CAS latency (2 and 3)
• Ambient temperature (TA): −20 to + 70°C
• Automatic precharge and controlled precharge
• CBR (Auto) refresh and self refresh
• ×16 organization
• Single 3.3 V ± 0.3 V power supply
• LVTTL compatible inputs and outputs
• 4,096 refresh cycles / 64 ms
• Burst termination by Burst stop command and Precharge command
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for
availability and additional information.
Document No. E0242N10 (Ver. 1.0)
Date Published December 2001 (K) Japan
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
1 page  
Block Diagram
CLK
CKE
Clock
Generator
Address
Mode
Register
/CS
/RAS
/CAS
/WE
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
µPD45128163-SU
Bank D
Bank C
Bank B
Bank A
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
DQM
DQ
Preliminary Data Sheet E0242N10
5
5 Page 
µPD45128163-SU
Self refresh entry command
(/CS, /RAS, /CAS, CKE = Low, /WE = High)
After the command execution, self refresh operation continues while
CKE remains low. When CKE goes high, the µPD45128163 exits the
self refresh mode.
During self refresh mode, refresh interval and refresh operation are
performed internally, so there is no need for external control.
Before executing self refresh, all banks must be precharged.
Fig.7 Self refresh entry command
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
Burst stop command
(/CS, /WE = Low, /RAS, /CAS = High)
This command can stop the current burst operation.
Fig.8 Burst stop command in Full Page
Mode
CLK
CKE H
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
No operation
(/CS = Low, /RAS, /CAS, /WE = High)
This command is not an execution command. No operations begin
or terminate by this command.
Fig.9 No operation
CLK
CKE
/CS
/RAS
/CAS
/WE
BA0(A13), BA1(A12)
A10
Add
H
Preliminary Data Sheet E0242N10
11
11 Page | ||
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| PDF Descargar | [ Datasheet PD45128163-SU.PDF ] | |
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