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PDF EF9345 Data sheet ( Hoja de datos )
| Número de pieza | EF9345 | |
| Descripción | HMOS2 SINGLE CHIP SEMI-GRAPHIC DISPLAY PROCESSOR | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de EF9345 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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EF9345
HMOS2 SINGLE CHIP SEMI-GRAPHIC
DISPLAY PROCESSOR
. SINGLE CHIP LOW-COST COLOR CRT
CONTROLLER
. TV STANDARD COMPATIBLE (50Hz or 60Hz)
. 2 SCREEN FORMATS :
. - 25 (or 21) ROWS OF 40 CHARACTERS
- 25 (or 21) ROWS OF 80 CHARACTERS
ON-CHIP 128 ALPHANUMERIC AND 128
SEMI-GRAPHIC CHARACTER GENERATOR
TWO STANDARD OPTIONS AVAILABLE FOR
. ALPHANUMERIC SETS (EF9345-R003 IS NO
MORE AVAILABLE)
EASY EXTENSION OF USER DEFINED AL-
. PHANUMERIC OR SEMI-GRAPHIC SETS
(> 1 K CHARACTERS)
40 CHARACTERS/ROW ATTRIBUTES : FORE-
GROUND AND BACKGROUND COLOR, DOU-
BLE HEIGHT, DOUBLE WIDTH, BLINKING,
REVERSE, UNDERLINING, CONCEAL, IN-
. SERT, ACCENTUATION OF LOWER CASE
CHARACTERS
80 CHARACTERS/ROW ATTRIBUTES : UN-
DERLINING, BLINKING, REVERSE, COLOR
SELECT
. PROGRAMMABLE ROLL-UP, ROLL-DOWN
AND CURSOR DISPLAY
. ON-CHIP R, G, B, I VIDEO SHIFT REGISTERS
. EASY SYNCHRONIZATION WITH EXTER-
. NAL VIDEO-SOURCE : ON-CHIP PHASE
COMPARATOR
ADDRESS/DATA MULTIPLEXED BUS DI-
RECTLY COMPATIBLE WITH STANDARD MI-
CROCOMPUTERS SUCH AS 6801, 6301,
8048, 8051, ST9
. ADDRESSING SPACE : 16K x 8 OF GEN-
ERAL PURPOSE PRIVATE MEMORY
. EASY OF USE OF ANY LOW-COST MEM-
ORY COMPONENTS : ROM, SRAM, DRAM
DESCRIPTION
The EF9345, new advanced color CRT controller,
in conjunction with an additional standard memory
package allow full implementation of the complete
display control unit of a color or monochrome low-
cost termainl, thus significantly reducing IC cost
and PCB space.
DIP40
(Plastic Package)
ORDER CODE : EF9345P
PIN CONNECTIONS
VSS
OE
WE
ASM
HVS/HS
PC/VS
B
G
R
I
HP
CLK
SYNC IN
AS
DS
R/W
AD0
AD1
AD2
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 ADM0
39 ADM1
38 ADM2
37 ADM3
36 ADM4
35 ADM5
34 ADM6
33 ADM7
32 AM8
31 AM9
30 AM10
29 AM11
28 AM12
27 AM13
26 CS
25 AD7
24 AD6
23 AD5
22 AD4
21 AD3
March 1995
1/38
1 page  
EF9345
MEMORY INTERFACE
VCC = 5.0V ±5%, TA = 0 to + 70°C
Clock : fin = 12MHz ; Duty Cycle 40 to 60% ; tr, tf < 5ns
Reference Levels : VIL = 0.8V and VIH = 2V, VOL = 0.4V and VOH = 2.4V
Symbol
tELEL
tD
tEHEL
tELDV
tDA
tAVEL
tELAX
tCLAZ
tGHDX
tOZ
tGLDV
tQVWL
tWHQX
tWLWH
Ident. N°
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Parameter
Memory Cycle Time
Output Delay Time from CLK Rising Edge (ASM, OE, WE)
ASM High Pule Width
Memory Access Time from ASM Low
Output Delay Time from CLK Rising Edge (ADM(0:7), AM(8:13))
Address Setup Time to ASM
Address Hold Time from ASM
Address Off Time
Memory Hold Time
Data Off Time from OE
Memory OE Access Time
Data Setup Time (Write Cycle)
Data Hold Time (Write Cycle)
WE Pulse Width
Min.
120
30
55
10
30
30
110
Typ.
500
Max.
60
290
80
80
60
150
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Figure 1 : Test Load
VDD
Test
Point
CL
RL
MMD7000
R or equivalent
Table 1
Symbol
C
RL
R
AM(8:13)
ADM(0:7)
AD(0:7)
100pF
1kΩ
4.7kΩ
Other
Outputs
50pF
3.3kΩ
4.7kΩ
Figure 2 : Memory Interface Timing Diagram
T1
CLK
ASM
2
42
56
8
7
ADM (0:7)
READ ADDRESS
D IN
3
56
7
WRITE ADDRESS
5
AM (8:14)
OE
WE
2
29
11
10
12
D OUT
22
14
13
5/38
5 Page 
EF9345
MEMORY ORGANIZATION
Logical And Physical Addressing
The physical 16-Kbyte addressingspace is logicaly
partitioned by EF9345 into 40-byte buffers (Fig-
ure 8). More precisely, a logical address is given by
an X, Y, Z triplet where :
- X = (0 to 39) points to a byte inside a buffer,
- Y = (0, 1 ; 8 to 31) points to a buffer inside a
1 Kbyte blocks,
- Z = (0 to 15) points to a block.
Obviously, 1 K = 210 = 1024 cannot be exactly
divided by 40. Consequently, any block holds 25
full buffers and a 24-byte remainder. Provided that
the physical memory is a multiple of 2 Kbytes, the
remainders are paired in such a way as to make
available :
- A full buffer (Y = 1) in each even block,
- A partial buffer (Y = 1 ; X = 32 to 39) in each odd
block.
Figure 8 : Memory Row Buffer
X
8 32 39
X
8 32 39
DISTRICT
0
1
8
31
0
1
8
Y
31
0
1
8
BLOCK 0
(1Kbyte)
BLOCK 1
BLOCK 2
31
0
1
8
BLOCK 3
31
0
9
DISTRICT
Y
DISTRICT
120-BYTE ROW BUFFER
80-BYTE ROW BUFFER
Notes : - Row buffers lay indide a district
- At two or three successive block addresses (modulo 4)
- First block address is even
Pointers
Each X, Y and Z component of a logical address is
binary encoded and packed in two 8-bits registers.
Such a register pair is a pointer (Figure 9). EF9345
contains two pointers :
- R4, R5 : auxiliary pointer,
- R6, R7 : main pointer.
R5 and R7 have the same format. Each one holds
an X component and the two LSB’s of a Z compo-
nent. This packing induces a partitioning of Z in 4
districts of 4 blocks each.
R5, R7 points to a block number in a district. R4
and R6 have a slightly different format : Each one
holds a Y component and the LSB of the district
number. But R6 holds both district MSB
Figure 11 gives the logical to physical address
transcoding scheme performed on chip.
Figure 9 : Pointer Auto Incrementation
d1 d’1 d0
b0 b1 5
Y = (0, 1 ; 8 to 31)
43210
X = 0 to 39
43210
R6
MAIN
POINTER
R7
_ _ d’0
b’0 b’1 5
Y’ = (0, 1 ; 8 to 31)
43210
X’ = 0 to 39
43210
R4
AUXILIARY
POINTER
R5
0
39
0
2=0
4=0
6=0
8
1
1
3= 1
5= 1
7= 1
9
Z = (0 to 15)
3210
DB
1
X 31 Y 10 0 B 2
2
X incrementation
Modulo 40
Y incrementation
Modulo 24
3
Z incrementation/
decrementation
Modulo 4 on the
block number only
11/38
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EF9345.PDF ] | |
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