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EF6805U2 Schematic ( PDF Datasheet ) - STMicroelectronics

Teilenummer EF6805U2
Beschreibung 8-BIT MICROCOMPUTER UNIT
Hersteller STMicroelectronics
Logo STMicroelectronics Logo 




Gesamt 30 Seiten
EF6805U2 Datasheet, Funktion
EF6805U3
8-BIT MICROCOMPUTER UNIT
HARDWARE FEATURES
. 32 TTL/CMOS COMPATIBLE I/O LINES
. 24 BIDIRECTIONAL (8 lines are LED compati-
ble)
. 8 INPUT-ONLY
. 3776 BYTES OF USER ROM
. 112 BYTES OF RAM
. SELF-CHECK MODE
. ZERO-CROSSING DETECT/INTERRUPT
. INTERNAL 8-BIT TIMER WITH 7-BIT SOFT-
. WARE PROGRAMMABLE PRESCALER AND
CLOCK SOURCE
5V SINGLE SUPPLY
..SOFTWARE FEATURES
10 POWERFUL ADDRESSING MODES
BYTE EFFICIENT INSTRUCTION SET WITH
TRUE BIT MANIPULATION, BIT TEST, AND
BRANCH INSTRUCTIONS
. SINGLE INSTRUCTION MEMORY EXA-
MINE/CHANGE
. POWERFUL INDEXED ADDRESSING FOR
TABLES
. FULL SET OF CONDITIONAL BRANCHES
. MEMORY USABLE AS REGISTER/FLAGS
. COMPLETE DEVELOPMENT SYSTEM SUP-
PORT ON INICE
USER SELECTABLE OPTIONS
. 8 BIDIRECTIONAL I/O LINES WITH TTL OR
TTL/CMOS INTERFACE OPTION
. 8 BIDIRECTIONAL I/O LINES WITH TTL OR O-
PEN-DRAIN INTERFACE OPTION
. CRYSTAL OR LOW-COST RESISTOR OSCIL-
LATOR OPTION
. LOW VOLTAGE INHIBIT OPTION
. VECTORED INTERRUPTS : TIMER, SOFT-
WARE, AND EXTERNAL
. USER CALLABLE SELF-CHECK SUBROU-
TINES
D ESCR I PTI O N
The EF6805U3 Microcomputer Unit (MCU) is a
member of the 6805 Family of low-cost single-chip
Microcomputers. The 8-bit microcomputer contains
a CPU, on-chip CLOCK, ROM, RAM, I/O, and TI-
MER. It is designed for the user who needs an eco-
nomical microcomputer with the proven capabilities
of the 6800-based instruction set. A comparison of
the key features of several members of the 6805 Fa-
mily of Microcomputers is shown at the end of this
data sheet. The following are some of the hardware
and software highlights of the EF6805U3 MCU.
1
P
(PDIP40)
FN
(PLCC 44)
PIN CONNECTIONS
March 1989
1/31






EF6805U2 Datasheet, Funktion
EF6805U3
INPUT/OUTPUT LINES (PA0-PA7, PB0-PB7, PC0-
PC7, PD0-PD7) - These 32 liens are arranged into
four 8-bit ports (A, B, C, and D). Ports A, B, and C
are programmable as either inputs or outputs under
software control of the data direction registers
(DDRs). Port D is for digital input only and bit 6 may
be used for a second interrupt INT2. Refer to In-
put/Output Section and Interrupts Section for addi-
tional information.
MEMORY - The MCU is capable of addressing 4096
bytes of memory and I/O registers with its program
counter. The EF6805U3 MCU has implemented
4090 of these bytes. This consists of : 3776 user
ROM bytes, 192 self-check ROM bytes, 112 user
RAM bytes, 7 port I/O bytes, 2 timer registers, and
a miscellaneous register ; see figure 6 for the Ad-
dress map. The user ROM has been split into two
areas. The main user ROM area is from $080 to
$F37. The last 8 user ROM locations at the bottom
of memory are for the interrupt vectors.
Figure 6 : EF6805U3 MCU Address Map.
The MCU reserves the first-16 memory locations for
I/O features, of which 10 have been implemented.
These locations are used for the ports, the port
DDRs, the timer and the INT2 miscellaneous regis-
ter, and the 112 RAM bytes, 31 bytes are shared
with the stack area. The stack must be used with
care when data shares the stack area.
The shared stack area is used during the processing
of an interrupt or subroutine calls to save the
contents of the CPU state. The register contents are
pushed onto the stack in the order shown in figure
7. Since the stack pointer decrements during
pushes, the low order byte (PCL) of the program
counter is stacked first, then the high order four bits
(PCH) are stacked. This ensures that the program
counter is loaded correctly during pulls from the
stack since the stack pointer increments when it
pulls data from the stack. A subroutine call results
in only the program counter (PCL, PCH) contents
being pushed onto the stack ; the remaining CPU re-
gisters are not pushed.
* Caution : Data direction registers (DDRs) are write only, they read as $FF.
6/31

6 Page









EF6805U2 pdf, datenblatt
EF6805U3
Figure 14 : RESET Configuration.
External Reset Input - The MCU will be reset if a lo-
gical zero is applied to the RESET input for a period
longer than one machine cycle (tcyc). Under this type
of reset, the Schmitt trigger switches off at VIRES- to
provide an internal reset voltage.
Low-Voltage Inhibit (LVI) - The optional low-voltage
detection circuit causes a reset of the MCU if the po-
wer supply voltage falls below a certain level (VLVI).
The only requirement is that VCC remains at or below
the VLVI threshold for one tcyc minimum. In typical
applications, the VCC bus filter capacitor will elimi-
nate negative-going voltage glitches of less than
one tcyc. The output from the low-voltage detector is
connected directly to the internal reset circuitry. It al-
so forces the RESET pin low via a strong discharge
device through a resistor. The internal reset will be
removed once the power supply voltage rises above
a recovery level (VLVR), at which time a normal po-
wer-on-reset occurs.
INTERNAL CLOCK GENERATOR OPTIONS
The internal clock generator circuit is designed to re-
quire a minimum of external components. A crystal,
a resistor, a jumper wire, or an external signal may
be used to generate a system clock with various sta-
bility/cost tradeoffs. The oscillator frequency is inter-
nally divided by four to produce the internal system
clocks. A manufacturing mask option is used to se-
lect crystal or resistor operation.
The different connection methods are shown in fig-
ure 15. Crystal specifications and suggested PC
board layouts are given in figure 16. A resistor se-
lection graph is given in figure 17.
The crystal oscillator start-up time is a function of
many variables : crystal parameters (especially RS),
oscillator load capacitances, IC parameters, am-
bient temperature, and supply voltage. To ensure
rapid oscillator start up, neither the crystal charac-
teristics nor the load capacitances should exceed
recommendations.
When utilizing the on-board oscillator, the MCU
should remain in a reset condition (reset pin voltage
below VIRES+) until the oscillator has stabilized at its
operating frequency. Several factors are involved in
calculating the external reset capacitor required to
satisfy this condition ; the oscillator start-up voltage,
the oscillator stabilization time, the minimum VIRES+,
and the reset charging current specification.
Once VCC minimum is reached, the external RESET
capacitor will begin to charge at a rate dependent on
the capacitor value. The charging current is supplied
from VCC through a large resistor, so it appears al-
most like a constant current source until the reset
voltage rises above VIRES+. Therefore, the RESET
pin will charge at approximately :
(VIRES+).Cext = IRES.tRHL
Assuming the external capacitor is initially dischar-
ged.
12/31

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