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PDF EF6805P6 Data sheet ( Hoja de datos )
| Número de pieza | EF6805P6 | |
| Descripción | 8-BIT MICROCOMPUTER UNIT | |
| Fabricantes | STMicroelectronics | |
| Logotipo |  |
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EF6805U3
8-BIT MICROCOMPUTER UNIT
HARDWARE FEATURES
. 32 TTL/CMOS COMPATIBLE I/O LINES
. 24 BIDIRECTIONAL (8 lines are LED compati-
ble)
. 8 INPUT-ONLY
. 3776 BYTES OF USER ROM
. 112 BYTES OF RAM
. SELF-CHECK MODE
. ZERO-CROSSING DETECT/INTERRUPT
. INTERNAL 8-BIT TIMER WITH 7-BIT SOFT-
. WARE PROGRAMMABLE PRESCALER AND
CLOCK SOURCE
5V SINGLE SUPPLY
..SOFTWARE FEATURES
10 POWERFUL ADDRESSING MODES
BYTE EFFICIENT INSTRUCTION SET WITH
TRUE BIT MANIPULATION, BIT TEST, AND
BRANCH INSTRUCTIONS
. SINGLE INSTRUCTION MEMORY EXA-
MINE/CHANGE
. POWERFUL INDEXED ADDRESSING FOR
TABLES
. FULL SET OF CONDITIONAL BRANCHES
. MEMORY USABLE AS REGISTER/FLAGS
. COMPLETE DEVELOPMENT SYSTEM SUP-
PORT ON INICE
USER SELECTABLE OPTIONS
. 8 BIDIRECTIONAL I/O LINES WITH TTL OR
TTL/CMOS INTERFACE OPTION
. 8 BIDIRECTIONAL I/O LINES WITH TTL OR O-
PEN-DRAIN INTERFACE OPTION
. CRYSTAL OR LOW-COST RESISTOR OSCIL-
LATOR OPTION
. LOW VOLTAGE INHIBIT OPTION
. VECTORED INTERRUPTS : TIMER, SOFT-
WARE, AND EXTERNAL
. USER CALLABLE SELF-CHECK SUBROU-
TINES
D ESCR I PTI O N
The EF6805U3 Microcomputer Unit (MCU) is a
member of the 6805 Family of low-cost single-chip
Microcomputers. The 8-bit microcomputer contains
a CPU, on-chip CLOCK, ROM, RAM, I/O, and TI-
MER. It is designed for the user who needs an eco-
nomical microcomputer with the proven capabilities
of the 6800-based instruction set. A comparison of
the key features of several members of the 6805 Fa-
mily of Microcomputers is shown at the end of this
data sheet. The following are some of the hardware
and software highlights of the EF6805U3 MCU.
1
P
(PDIP40)
FN
(PLCC 44)
PIN CONNECTIONS
March 1989
1/31
1 page  
Figure 2 : TTL Equivalent Test Load (port B).
EF6805U3
Figure 3 : CMOS Equivalent Test Load (port A).
Figure 4 : TTL Equivalent Test Load (port A
andC).
Figure 5 : Open-drain Equivalent Test Load (port
C).
SIGNAL DESCRIPTION
The input and output signals for the MCU, shown in
figure 1, are described in the following paragraphs.
VCC AND VSS - Power is supplied to the MCU using
these two pins. VCC is power and VSS is the ground
connection.
INT - This pin provides the capability for asynchro-
nously applying an external interrupt to the MCU.
Refer to Interrupts Section for additional informa-
tion.
XTAL AND EXTAL - These pins provide control in-
put for theon-chip clock oscillator circuit. A crystal,
a resistor, or an external signal, depending on user
selectable manufacturing mask option, can be
connected to these pins to provide a system clock
with various degrees of stability/cost tradeoffs. Lead
length and stray capacitance on these two pins
should be minimized. Refer to Internal Clock Gen-
erator Options Section for recommendations about
these inputs.
NOTE : Pin 7 in DIL package/pin 8 in PLCC
package is connected to internal protection.
TIMER - The pin allows an external input to be used
to control the internal timer circuitry and also to ini-
tiate the self test program. Refer to Timer Section for
additional information about the timer circuitry.
RESET - This pin allows resetting of the MCU at
times other than the automatic resetting capability
already in the MCU. The MCU can be reset by pul-
ling RESET low. Refer to Resets Section for addi-
tional information.
5/31
5 Page 
EF6805U3
TIMER SELF-CHECK SUBROUTINE - The timer
self-check is called at location $F6D and returns with
the Z bit cleared if any error was found ; otherwise
Z = 1.
In order to work correctly as a user subroutine, the
internal 2 clock must be the clocking source and in-
terrupts must be disabled. Also, on exit, the clock is
running and the interrupt mask is not set so the caller
must protect from interrupts if necessary.
The A and X register contents are lost. This routine
sets the prescaler for divide-by-128 and the timer
data register is cleared. The X register is configured
to count down the same as the timer data register.
The two registers are then compared every 128 cy-
cles until they both count down to zero. Any mis-
match during the count down is considered as an er-
ror. The A and X registers are cleared on exit from
the routine.
RESET
The MCU can be reset three ways : by initial powe-
rup, by the external reset input (RESET) and by an
optional internal low-voltage detect circuit. The RE-
SET input consists mainly of a Schmitt trigger which
senses the RESET line logic level. A typical reset
Schmitt trigger hysteresis curve is shown in figure
12. The Schmitt trigger provides an internal reset
voltage if it senses a logical zero on the RESET pin.
Power-On Reset (POR) - An internal reset is gene-
rated upon powerup that allows the internal clock
generator to stabilize. A delay of tRHL milliseconds
is required before allowing the RESET input to go
high. Refer to the power and reset timing diagram
of figure 13. Connecting a capacitor to the RESET
input (as illustrated in figure 14) typically provides
sufficient delay. During powerup, the Schmitt trigger
switches on (removes reset) when RESET rises to
VIRES+.
Figure 12 : Typical Reset Schmitt Trigger Hysteresis.
Figure 13 : Power and Reset Timing.
11/31
11 Page | ||
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| PDF Descargar | [ Datasheet EF6805P6.PDF ] | |
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