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PDF EF4442 Data sheet ( Hoja de datos )
| Número de pieza | EF4442 | |
| Descripción | ARINC 429 Multi-channel Buffer Receiver (RTA) (N Channel/ Silicon Gate) | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• Four Independent Receivers
• OneTransmitter in A Mode
• Direct 6800 Microprocessor Interface
• 8-bit Data Bus
• ARINC Interface: “1” and “0” Lines, RZ Code
• Software Label Control in A Mode
• Parity Control: Odd or No Parity
• Interrupt Capability in A Mode
• Test Mode Capability
Description
The EF4442 is a reception interface for 4 ARINC 429 channels.
Two models of operation are provided:
• When in A mode, the circuit can be considered as a peripheral of an EF 6800 or
EF6802 microprocessor and is totally software programmable (for example, for
test purposes).
• When in B mode, the parameters are hardware programmed. Reading the
registers which contain messages is only possible (max. scan frequency: 2 MHz).
Screening Quality
This product is manufactured in full compliance with either:
• NFC 96883 class G
• MIL-STD-883 class B
• According to Atmel standards
Application Note
Ask for application note: “General application principles EF4442(RTA)”
C Suffix
DIL 28
Ceramic Side Brazed package
ARINC 429
Multi-channel
Buffer Receiver
(RTA)
(N Channel,
Silicon Gate)
EF4442
P Suffix
DIP 28
Plastic Package
Rev. 2112A–HIREL–11/02
1
1 page  
EF4442
Input Register
Label Register
Buffer Register
This 32-bit shift register receives the data corresponding to the messages. The mes-
sage received is transferred into the registers on its output side if:
• a gap detection signal has previously occurred,
• the registers which will receive the transferred data are not being read,
• the parity of the received message is correct if the circuit is programmed with the
parity check enabled,
• the enable bit of the synchronization/enable register is set to 1 (A mode only),
• in A mode, the first eight bits received correspond to the programmed label (cf.
description of label register).
In A mode, this eight-bit register is programmed by the microprocessor. It contains the
label to be recognized.
In B mode, this register receives the first eight bits of the received message transferred
from the input register.
In this case, this register may be read by the external automatic scanning device.
This 24-bit register receives data transferred from the input register.
It may be read by the microprocessor in A mode or by the external automatic scanning
device in B mode.
Circuit Operation
Logic Convention
Operation of a Receive
Channel
Data Acquisition
“1” (high state) = most positive level
“0” (low state) = most negative level
Serial data is received on the “low” and the “high” lines (Hi and Li inputs). The Clock is
reconstructed by OR-ing these inputs. Data is then directed towards a 32-bit shift regis-
ter. Parity is computed. The reconstructed clock fall edge resets the message
synchronization counter. This counter is incremented on each Ø: 8 clock period and
delivers a word synchronization signal (gap) as described below (Figure 2) when read-
ing a programmed value.
Figure 2. Gap Detection
Clock
max
gap
Counter
0
Synchro
Predetermined value
The predetermined value together with an enable bit is loaded in the internal syn-
chro/validation register when in A mode; it is chosen between two hardware
programmed values when in B mode, according to the IRQ/V pin.
2112A–HIREL–11/02
5
5 Page 
EF4442
The total thermal resistance of a package (qJA) can be separated into two components,
qJC and qCA, representing the barrier to heat flow from the semiconductor junction to the
package (case), surface (qJC) and from the case to the outside ambient (qCA). These
terms are related by the equation:
qJA = qJC + qCA
(4)
qJC is device related and cannot be influenced by the user. However, qCA is user depen-
dent and can be minimized by such thermal management techniques as heat sinks,
ambient air cooling and thermal convection. Thus, good thermal management on the
part of the user can significantly reduce qCA so that qJA approximately equals qJC. Substi-
tution of qJC for qJA in equation (1) will result in a lower semiconductor junction
temperature.
Table 6. Recommended Static Operating Conditions
Symbol
Parameter
Min Max Unit
VIH Input High Voltage
VIL Input Low Voltage
VCC Supply Voltage
2.0 5.25
-0.3 0.8
4.75 5.25
V
V
V
Table 7. Static Characteristics
(VCC = 5.0V ± 5%; VSS = 0V; -55°C < TC < + 125°C)
Symbol
Characteristics
VIH Input high voltage (except MODE, IRQ/V)
VIL Input low voltage (except MODE, IRQ/V)
Iin Input state leakage current (except MODE, IRQ/V)
(VIN = 0.4 to 5.25V)
ITSI Three state leakage current N0-N1, D0-D7
(VIN = 0.4 to 2.4V)
VOH Output high voltage
(ILoad = -250 µA) N0-N1, D0-D7
(ILoad = +10 µA) IRQ/V
VOL Output high voltage
(ILoad = 1.6 mA) N0-N1, D0-D7
(ILoad = 3.2 mA) IRQ/V
Cin Capacitance
(Vin= 0, TC = 25°C, f = 1 MHz)
(except MODE, IRQ/V)
RH External high programming impedance
MODE, IRQ/V, (Cload £ 20pF)
Scan frequency = f clock: 8)
RL External low programming impedance
Mode, IRQ/V (Cload £ 20 pF)
Scan frequency = f clock: 8)
Min Typ Max Unit
2.2
VCC
V
-0.3 0.8 V
-10 µA
-10 10 µA
2.4
VCC
V
2.4 VCC
0.4 V
10 pF
10 K
W
10 W
2112A–HIREL–11/02
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet EF4442.PDF ] | |
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