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PDF EDS2508APTA-75TI Data sheet ( Hoja de datos )
| Número de pieza | EDS2508APTA-75TI | |
| Descripción | 256M bits SDRAM WTR (Wide Temperature Range) | |
| Fabricantes | Elpida Memory | |
| Logotipo |  |
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PRELIMINARY DATA SHEET
256M bits SDRAM
WTR (Wide Temperature Range)
EDS2504APTA-TI (64M words × 4 bits)
EDS2508APTA-TI (32M words × 8 bits)
EDS2516APTA-TI (16M words × 16 bits)
Description
Pin Configurations
The EDS2504AP is a 256M bits SDRAM organized as
16,777,216 words × 4 bits × 4 banks. The EDS2508
AP is a 256M bits SDRAM organized as 8,388,608
words × 8 bits × 4 banks. The EDS2516 AP is a 256M
bits SDRAM organized as 4194304 words × 16 bits × 4
banks. All inputs and outputs are referred to the rising
edge of the clock input. It is packaged in standard 54-
pin plastic TSOP (II).
Features
• 3.3V power supply
• Clock frequency: 133MHz (max.)
• LVTTL interface
• Single pulsed /RAS
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8, full page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
: DQM (EDS2504/08AP)
: UDQM, LDQM (EDS2516AP)
• Refresh cycles: 8192 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• Ambient temperature range: –40 to +85°C
/xxx indicates active low signal.
54-pin TSOP
VDD VDD VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VSSQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VSSQ
NC NC DQ7
VDD VDD VDD
NC NC LDQM
/WE /WE /WE
/CAS /CAS /CAS
/RAS /RAS /RAS
/CS /CS /CS
BA0 BA0 BA0
BA1 BA1 BA1
A10 A10 A10
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD VDD VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS VSS VSS
53 DQ15 DQ7 NC
52 VSSQ VSSQ VSSQ
51 DQ14 NC NC
50 DQ13 DQ6 DQ3
49 VDDQ VDDQ VDDQ
48 DQ12 NC NC
47 DQ11 DQ5 NC
46 VSSQ VSSQ VSSQ
45 DQ10 NC NC
44 DQ9 DQ4 DQ2
43 VDDQ VDDQ VDDQ
42 DQ8 NC NC
41 VSS VSS VSS
40 NC NC NC
39 UDQM DQM DQM
38 CLK CLK CLK
37 CKE CKE CKE
36 A12 A12 A12
35 A11 A11 A11
34 A9 A9 A9
33 A8 A8 A8
32 A7 A7 A7
31 A6 A6 A6
30 A5 A5 A5
29 A4 A4 A4
28 VSS VSS VSS
X 16
X8
X4
(Top view)
A0 to A12, Address input
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
/CS Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write enable
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0248E10 (Ver. 1.0)
Date Published March 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
1 page  
EDS2504APTA/08APTA/16APTA-TI
DC Characteristics 1 (TA = –40 to +85°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
max.
/CAS latency
Symbol Grade × 4 × 8 × 16 Unit Test condition
Notes
Operating current
ICC1
-7A 130 130 135
ICC1
-75 110 110 115
Standby current in power
down
Standby current in power
down (input signal stable)
ICC2P
ICC2PS
Standby current in non
power down
Standby current in non
power down (input signal
stable)
ICC2N
ICC2NS
Active standby current in
power down
Active standby current in
power down (input signal
stable)
Active standby current in
non power down
Active standby current in
non power down (input
signal stable)
ICC3P
ICC3PS
ICC3N
ICC3NS
Burst operating current ICC4
333
222
20 20 20
999
444
333
30 30 30
15 15 15
130 135 145
mA
Burst length = 1
tRC = min.
mA
Burst length = 1
tRC = min.
1, 2, 3
mA CKE = VIL, tCK = min. 6
mA CKE = VIL, tCK = ∞ 7
mA
CKE, /CS = VIH,
tCK = min.
4
mA
CKE = VIH, tCK = ∞,
/CS = VIH
8
mA CKE = VIL, tCK = min. 1, 2, 6
mA CKE = VIL, tCK = ∞ 2, 7
mA
CKE, /CS = VIH,
tCK = min.
1, 2, 4
mA
CKE = VIH, tCK = ∞,
/CS = VIH
2, 8
mA tCK = min., BL = 4 1, 2, 5
Refresh current
ICC5
-7A 250 250 250
mA tRC = min.
3
ICC5
-75 220 220 220
mA tRC = min.
Self refresh current
ICC6
333
mA
VIH ≥ VDD – 0.2V
VIL ≤ 0.2V
Notes: 1. ICC depends on output load condition when the device is selected. ICC (max.) is specified at the output
open condition.
2. One bank operation.
3. Input signals are changed once per one clock.
4. Input signals are changed once per two clocks.
5. Input signals are changed once per four clocks.
6. After power down mode, CLK operating current.
7. After power down mode, no CLK operating current.
8. Input signals are VIH or VIL fixed.
Preliminary Data Sheet E0248E10 (Ver. 1.0)
5
5 Page 
[Output High Current (IOH)]
VOUT (V)
3.45
3.3
3
2.6
2.4
2
1.8
1.65
1.5
1.4
1
0
250
200
IOH
min. (mA)
—
—
0
–21
–34
–59
–67
–73
–78
–81
–89
–93
EDS2504APTA/08APTA/16APTA-TI
IOH
max. (mA)
–3
–28
–75
–130
–154
–197
–227
–248
–270
–285
–345
–503
150
min.
max.
100
50
0
0 0.5 1 1.5 2 2.5 3 3.5
VOUT (V)
Output High Current (IOH)
Preliminary Data Sheet E0248E10 (Ver. 1.0)
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet EDS2508APTA-75TI.PDF ] | |
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