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EDS2504ACTA Schematic ( PDF Datasheet ) - Elpida Memory

Teilenummer EDS2504ACTA
Beschreibung 256M bits SDRAM
Hersteller Elpida Memory
Logo Elpida Memory Logo 




Gesamt 30 Seiten
EDS2504ACTA Datasheet, Funktion
DATA SHEET
256M bits SDRAM
EDS2504ACTA, EDS2504APTA (64M words × 4 bits)
EDS2508ACTA, EDS2508APTA (32M words × 8 bits)
EDS2516ACTA, EDS2516APTA (16M words × 16 bits)
Description
Pin Configurations
The EDS2504AC/AP is a 256M bits SDRAM organized
as 16,777,216 words × 4 bits × 4 banks. The EDS2508
AC/AP is a 256M bits SDRAM organized as 8,388,608
words × 8 bits × 4 banks. The EDS2516 AC/AP is a
256M bits SDRAM organized as 4194304 words × 16
bits × 4 banks. All inputs and outputs are referred to
the rising edge of the clock input. It is packaged in
standard 54-pin plastic TSOP (II).
Features
3.3V power supply
Clock frequency: 133MHz (max.)
LVTTL interface
Single pulsed /RAS
4 banks can operate simultaneously and
independently
Burst read/write operation and burst read/single write
operation capability
Programmable burst length* (BL): 1, 2, 4, 8
2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
Interleave (BL = 1, 2, 4, 8)
Programmable /CAS latency (CL): 2, 3
Byte control by DQM
: DQM (EDS2504AC/AP, EDS2508AC/AP)
: UDQM, LDQM (EDS2516AC/AP)
Refresh cycles: 8192 refresh cycles/64ms
2 variations of refresh
Auto refresh
Self refresh
Note: EDS2504AP/08AP/16AP is supported full page
function.
/xxx indicates active low signal.
Index
Index
EDS2504AC/08AC/16AC
EDS2504AP/08AP/16AP
54-pin TSOP
VDD VDD VDD
NC DQ0 DQ0
VDDQ VDDQ VDDQ
NC NC DQ1
DQ0 DQ1 DQ2
VSSQ VSSQ VSSQ
NC NC DQ3
NC DQ2 DQ4
VDDQ VDDQ VDDQ
NC NC DQ5
DQ1 DQ3 DQ6
VSSQ VSSQ VSSQ
NC NC DQ7
VDD VDD VDD
NC NC LDQM
/WE /WE /WE
/CAS /CAS /CAS
/RAS /RAS /RAS
/CS /CS /CS
BA0 BA0 BA0
BA1 BA1 BA1
A10 A10 A10
A0 A0 A0
A1 A1 A1
A2 A2 A2
A3 A3 A3
VDD VDD VDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54 VSS VSS VSS
53 DQ15 DQ7 NC
52 VSSQ VSSQ VSSQ
51 DQ14 NC NC
50 DQ13 DQ6 DQ3
49 VDDQ VDDQ VDDQ
48 DQ12 NC NC
47 DQ11 DQ5 NC
46 VSSQ VSSQ VSSQ
45 DQ10 NC NC
44 DQ9 DQ4 DQ2
43 VDDQ VDDQ VDDQ
42 DQ8 NC NC
41 VSS VSS VSS
40 NC NC NC
39 UDQM DQM DQM
38 CLK CLK CLK
37 CKE CKE CKE
36 A12 A12 A12
35 A11 A11 A11
34 A9 A9 A9
33 A8 A8 A8
32 A7 A7 A7
31 A6 A6 A6
30 A5 A5 A5
29 A4 A4 A4
28 VSS VSS VSS
X 16
X8
X4
(Top view)
A0 to A12, Address input
BA0, BA1 Bank select address
DQ0 to DQ15 Data-input/output
/CS Chip select
/RAS
Row address strobe
/CAS
Column address strobe
/WE Write enable
DQM
CKE
CLK
VDD
VSS
VDDQ
VSSQ
NC
Input/output mask
Clock enable
Clock input
Power for internal circuit
Ground for internal circuit
Power for DQ circuit
Ground for DQ circuit
No connection
Document No. E0110E30 (Ver. 3.0)
Date Published November 2001 (K) Japan
URL: http://www.elpida.com
C Elpida Memory, Inc. 2001






EDS2504ACTA Datasheet, Funktion
EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
Symbol
ILI
ILO
VOH
VOL
min.
–1
–1.5
2.4
max.
1
1.5
0.4
Unit Test condition
Notes
µA 0 VIN VDD
µA 0 VOUT VDD, DQ = disable
V IOH = –4 mA
V IOL = 4 mA
Pin Capacitance (TA = 25°C, VDD, VDDQ = 3.3V ± 0.3V)
Parameter
Symbol Pins
min. Typ
max.
Unit
Input capacitance
CI1 CLK
2.5 —
3.5 pF
Data input/output capacitance
CI2
CI/O
Address, CKE, /CS, /RAS,
/CAS, /WE, DQM,
DQ
2.5
4
3.8 pF
6.5 pF
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. Measurement condition: f = 1MHz, 1.4V bias, 200mV swing.
3. DQM = VIH to disable DOUT.
4. This parameter is sampled and not 100% tested.
Notes
1, 2, 4
1, 2, 4
1, 2, 3, 4
AC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 3.3V ± 0.3V, VSS, VSSQ = 0V)
-7A -75
Parameter
Symbol
min.
min.
max.
Unit
System clock cycle time
tCK 7.5 7.5 —
ns
CLK high pulse width
tCH 2.5 2.5 —
ns
CLK low pulse width
tCL 2.5 2.5 —
ns
Access time from CLK
tAC — — 5.4
ns
Data-out hold time
tOH 2.7 2.7 —
ns
CLK to Data-out low impedance
tLZ
1
1
ns
CLK to Data-out high impedance
tHZ
5.4
ns
Input setup time
tSI 1.5 1.5 —
ns
Input hold time
tHI 0.8 0.8 —
ns
Ref/Active to Ref/Active command period tRC 60 67.5 —
ns
Active to Precharge command period tRAS
45
45
120000
ns
Active command to column command
(same bank)
tRCD
15
20
ns
Precharge to active command period tRP 15 20 —
Write recovery or data-in to precharge
lead time
tDPL
15
15
ns
ns
Last data into active latency
tDAL
2CLK + 15ns 2CLK + 20ns —
Active (a) to Active (b) command period tRRD
15
15
ns
Transition time (rise and fall)
tT
0.5 0.5 5
ns
Refresh period
(8192 refresh cycles)
tREF
64
ms
Notes: 1. AC measurement assumes tT = 0.5ns. Reference level for timing of input signals is 1.4V.
2. Access time is measured at 1.4V. Load condition is CL = 50pF.
3. tLZ (min.) defines the time at which the outputs achieves the low impedance state.
4. tHZ (max.) defines the time at which the outputs achieves the high impedance state.
Notes
1
1
1
1, 2
1, 2
1, 2, 3
1, 4
1
1
1
1
1
1
1
1
Data Sheet E0110E30 (Ver. 3.0)
6

6 Page









EDS2504ACTA pdf, datenblatt
EDS2504ACTA/08ACTA/16ACTA, EDS2504APTA/08APTA/16APTA
Block Diagram
CLK
CKE
Clock
Generator
Address
Mode
Register
/CS
/RAS
/CAS
/WE
Row
Address
Buffer
&
Refresh
Counter
Column
Address
Buffer
&
Burst
Counter
Bank 3
Bank 2
Bank 1
Bank 0
Sense Amplifier
Column Decoder &
Latch Circuit
Data Control Circuit
DQM
DQ
Data Sheet E0110E30 (Ver. 3.0)
12

12 Page





SeitenGesamt 30 Seiten
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