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Teilenummer | EDS1232CABB |
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Beschreibung | 128M bits SDRAM | |
Hersteller | Elpida Memory | |
Logo | ||
Gesamt 30 Seiten PRELIMINARY DATA SHEET
128M bits SDRAM
EDS1232CABB, EDS1232CATA (4M words × 32 bits)
Description
The EDS1232CA is a 128M bits SDRAM organized as
1,048,576 words × 32 bits × 4 banks. All inputs and
outputs are synchronized with the positive edge of the
clock.
They are packaged in 90-ball FBGA, 86-pin plastic
TSOP (II).
Features
• 2.5V power supply
• Clock frequency: 133MHz (max.)
• Single pulsed /RAS
• ×32 organization
• 4 banks can operate simultaneously and
independently
• Burst read/write operation and burst read/single write
operation capability
• Programmable burst length (BL): 1, 2, 4, 8 and full
page
• 2 variations of burst sequence
Sequential (BL = 1, 2, 4, 8)
Interleave (BL = 1, 2, 4, 8)
• Programmable /CAS latency (CL): 2, 3
• Byte control by DQM
• Refresh cycles: 4096 refresh cycles/64ms
• 2 variations of refresh
Auto refresh
Self refresh
• FBGA package is lead free solder (Sn-Ag-Cu)
Document No. E0247E40 (Ver. 4.0)
Date Published July 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
EDS1232CABB, EDS1232CATA
DC Characteristics (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
Parameter
/CAS latency
Symbol Grade max.
Unit Test condition
Notes
Operating current
(CL = 2)
(CL = 3)
IDD1
IDD1
-75 105
-1A 100
-75 105
-1A 100
mA Burst length = 1
tRC ≥ tRC (min.)
IO = 0mA
mA One bank active
1
Standby current in power down
Standby current in power down
(input signal stable)
IDD2P
IDD2PS
Standby current in non power
down
IDD2N
Standby current in non power
down
(input signal stable)
Active standby current in power
down
Active standby current in power
down (input signal stable)
IDD2NS
IDD3P
IDD3PS
Active standby current in non
power down
IDD3N
Active standby current in non
power down
(input signal stable)
Burst operating current
IDD3NS
IDD4
Refresh current
IDD5
Self refresh current
Self refresh current
(L-version)
IDD6
IDD6
-75
-1A
-75
-1A
-xxL
1
1
20
8
5
4
25
15
150
130
210
200
2.0
0.6
mA CKE ≤ VIL (max.) tCK = 15ns
mA CKE ≤ VIL (max.) tCK = ∞
CKE ≥ VIH (min.) tCK = 15ns
mA
CS ≥ VIH (min.)
Input signals are changed one
time during 30ns
mA CKE ≥ VIH (min.) tCK = ∞
mA CKE ≤ VIL (max.) tCK = 15ns
mA CKE ≤ VIL (max.), tCK = ∞
CKE ≥ VIH (min.), tCK = 15 ns,
mA
/CS ≥ VIH (min.),
Input signals are changed one
time during 30ns.
mA CKE ≥ VIH (min.), tCK = ∞,
mA
tCK ≥ tCK (min.),
IO = 0mA, All banks active
mA tRC ≥ tRC (min.)
mA
VIH ≥ VDD − 0.2V,
VIL ≤ GND + 0.2V
mA
2
3
Notes: 1. IDD1 depends on output loading and cycle rates. Specified values are obtained with the output open. In
addition to this, IDD1 is measured condition that addresses are changed only one time during tCK (min.).
2. IDD4 depends on output loading and cycle rates. Specified values are obtained with the output open.
In addition to this, IDD4 is measured condition that addresses are changed only one time during tCK
(min.).
3. IDD5 is measured on condition that addresses are changed only one time during tCK (min.).
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 2.5V±0.2V, VSS, VSSQ = 0V)
Parameter
Input leakage current
Output leakage current
Output high voltage
Output low voltage
Symbol
ILI
ILO
VOH
VOL
min.
–1.0
–1.5
2.0
—
max.
1.0
1.5
—
0.4
Unit Test condition
Notes
µA
0 = VIN = VDDQ, VDDQ = VDD,
All other pins not under test = 0V
µA 0 = VIN = VDDQ DOUT is disabled
V IOH = –1mA
V IOL = 1mA
Preliminary Data Sheet E0247E40 (Ver. 4.0)
6
6 Page EDS1232CABB, EDS1232CATA
Command Operation
Mode register set command (/CS, /RAS, /CAS, /WE)
The Synchronous DRAM has a mode register that defines how the device operates. In this command, A0 through
A11 are the data input pins. After power on, the mode register set command must be executed to initialize the
device. The mode register can be set only when all banks are in idle state. During 2CLK (tRSC) following this
command, the Synchronous DRAM cannot accept any other commands.
CLK
CKE H
/CS
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Add
Mode Register Set Command
Activate command (/CS, /RAS = Low, /CAS, /WE = High)
The Synchronous DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA0
and BA1 and a row address selected by A0 through A11. This command corresponds to a conventional DRAM's
/RAS falling.
CLK
CKE
/CS
H
/RAS
/CAS
/WE
BA0, BA1
(Bank select)
A10
Row
Add Row
Row Address Strobe and Bank Activate Command
Preliminary Data Sheet E0247E40 (Ver. 4.0)
12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ EDS1232CABB Schematic.PDF ] |
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