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Teilenummer | EDE5116GBSA |
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Beschreibung | 512M bits DDR-II SDRAM | |
Hersteller | Elpida Memory | |
Logo | ||
Gesamt 30 Seiten PRELIMINARY DATA SHEET
512M bits DDR-II SDRAM
EDE5104GBSA (128M words × 4 bits)
EDE5108GBSA (64M words × 8 bits)
EDE5116GBSA (32M words × 16 bits)
Description
The EDE5104GB is a 512M bits DDR-II SDRAM
organized as 33,554,432 words × 4 bits × 4 banks.
The EDE5108GB is a 512M bits DDR-II SDRAM
organized as 16,777,216 words × 8 bits × 4 banks.
It packaged in 64-ball µBGA package.
The EDE5116GB is a 512M bits DDR-II SDRAM
organized as 8,388,608 words × 16 bits × 4 banks.
It is packaged in 84-ball µBGA package.
Features
• 1.8V power supply
• Double-data-rate architecture: two data transfers per
clock cycle
• Bi-directional, differential data strobe (DQS and
/DQS) is transmitted/received with data, to be used in
capturing data at the receiver
• DQS is edge aligned with data for READs: center-
aligned with data for WRITEs
• Differential clock inputs (CK and /CK)
• DLL aligns DQ and DQS transitions with CK
transitions
• Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
• Four internal banks for concurrent operation
• Data mask (DM) for write data
• Burst lengths: 4, 8
• /CAS Latency (CL): 3, 4, 5
• Auto precharge operation for each burst access
• Auto refresh and self refresh modes
• 7.8µs average periodic refresh interval
• 1.8V (SSTL_18 compatible) I/O
• Posted CAS by programmable additive latency for
better command and data bus efficiency
• Off-Chip-Driver Impedance Adjustment and On-Die-
Termination for better signal quality
• Programmable RDQS, /RDQS output for making × 8
organization compatible to × 4 organization
• /DQS, (/RDQS) can be disabled for single-ended
Data Strobe operation.
• µBGA package is lead free solder (Sn-Ag-Cu)
Document No. E0249E30 (Ver. 3.0)
Date Published August 2002 (K) Japan
URL: http://www.elpida.com
Elpida Memory, Inc. 2002
EDE5104GBSA, EDE5108GBSA, EDE5116GBSA
DC Characteristics 1 (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V)
max.
Parameter
Symbol Grade × 4, × 8 × 16
Unit Test condition
Operating current
(ACT-PRE)
IDD0
TBD
one bank; tRC = tRC (min.) ; tCK = tCK (min.) ; DQ,
TBD
mA
DM, and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock
cycle
Operating current
(ACT-READ-PRE)
IDD1
TBD
one bank; Burst = 4; tRC = tRC (min.) ;
TBD
mA
CL = 4; tCK = tCK (min.) ; IOUT = 0mA;
address and control inputs changing once per clock
cycle
Precharge power-down
standby current
IDD2P
TBD
TBD
mA
all banks idle; power-down mode; CKE = VIL (max.);
tCK = tCK (min.)
Idle standby current IDD2N
TBD
/CS = VIH (min.); all banks idle; CKE = VIH (min.);
TBD mA tCK = tCK (min.) ; address and control inputs
changing once per clock cycle
Active power-down
standby current
IDD3P
TBD
one bank active; power-down mode; CKE = VIL
TBD mA (max.);
tCK = tCK (min.)
Active standby current IDD3N
TBD
one bank; active;/CS = VIH (min.);
CKE = VIH (min.); tRC = tRAS max; tCK = tCK
TBD mA (min.); DQ, DM, and DQS inputs changing twice per
clock cycle; address and control inputs changing
once per clock cycle
Operating current
IDD4R
(Burst read operating)
TBD
one bank; Burst = 4; burst; address and control
TBD
mA
inputs changing once per clock cycle; DQ and DQS
outputs changing twice per clock cycle; CL = 4; tCK
= tCK (min.) ; IOUT = 0mA
Operating current
(Burst write operating) IDD4W
TBD
one bank; Burst = 4; writes; continuous burst;
address and control inputs changing once per clock
TBD mA cycle; DQ and DQS inputs changing twice per clock
cycle; CL = 4;
tCK = tCK (min.)
Auto-refresh current IDD5
TBD
TBD mA tRC = tRFC (min.)
Self-refresh current IDD6
TBD
TBD mA Self Refresh Mode; CKE = 0.2V
Operating current
(Bank interleaving)
IDD7
TBD
Four bank interleaving READs (BL4) with auto
TBD
mA
precharge, tRC = tRC (min.); Address and control
inputs change during Active, READ, or WRITE
commands.
DC Characteristics 2 (TA = 0 to +70°C, VDD, VDDQ = 1.8V ± 0.1V)
Parameter
Symbol
Unit
Minimum required output pull-up under AC
test load
VOH
Maximum required output pull-down under
AC test load
VOL
VTT + 0.603
VTT – 0.603
V
V
Output timing measurement reference level VOTR
0.5 × VDDQ
V
Output minimum sink DC current
IOL
+13.4
mA
Output minimum source DC current
IOH
–13.4
mA
Note: 1. The VDDQ of the device under test is referenced.
2. VDDQ = 1.7V; VOUT = 1.42V.
3. VDDQ = 1.7V; VOUT = 0.28V.
4. The DC value of VREF applied to the receiving device is expected to be set to VTT.
5. After OCD calibration to 18Ω at TA = 25°C, VDD = VDDQ = 1.8V.
Notes
5
5
1
3, 4, 5
2, 4, 5
Preliminary Data Sheet E0249E30 (Ver. 3.0)
6
6 Page EDE5104GBSA, EDE5108GBSA, EDE5116GBSA
DM, UDM and LDM (input pins)
DM is an input mask signal for write data. In 32M × 16 products, UDM and LDM control upper byte (DQ8 to DQ15)
and lower byte (DQ0 to DQ7). Input data is masked when DM is sampled High coincident with that input data during
a Write access. DM is sampled on both edges of DQS. Although DM pins are input only, the DM loading matches
the DQ and DQS loading. For ×8 configuration, DM function will be disabled when RDQS function is enabled by
EMRS.
DQ (input/output pins)
Bi-directional data bus.
DQS, /DQS, UDQS, /UDQS, LDQS, /LDQS (input/output pins)
Output with read data, input with write data for source synchronous operation. In 32M × 16 products, UDQS, /UDQS
and LDQS, /LDQS control upper byte (DQ8 to DQ15) and lower byte (DQ0 to DQ7). Edge-aligned with read data,
centered in write data. Used to capture write data. /DQS can be disabled by EMRS.
RDQS, /RDQS (output pins)
Differential Data Strobe for READ operation only. DM and RDQS functions are switch able by EMRS. These pins
exist only in ×8 configuration. /RDQS output will be disabled when /DQS is disabled by EMRS.
ODT (input pins)
ODT (On Die Termination control) is a registered High signal that enables termination resistance internal to the DDR
II SDRAM. When enabled, ODT is only applied to each DQ, DQS, /DQS, RDQS, /RDQS, and DM signal for × 4, × 8
configurations. For × 16 configuration, ODT is applied to each DQ, UDQS, /UDQS, LDQS, /LDQS, UDM, and LDM
signal. The ODT pin will be ignored if the Extended Mode Register (EMRS) is programmed to disable ODT.
VDD, VSS, VDDQ, VSSQ (power supply)
VDD and VSS are power supply pins for internal circuits. VDDQ and VSSQ are power supply pins for the output
buffers.
VDDL and VSSDL (power supply)
VDDL and VSSDL are power supply pins for DLL circuits.
VREF (Power supply)
SSTL_18 reference voltage: (0.50 ± 0.01) × VDDQ
Preliminary Data Sheet E0249E30 (Ver. 3.0)
12
12 Page | ||
Seiten | Gesamt 30 Seiten | |
PDF Download | [ EDE5116GBSA Schematic.PDF ] |
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