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PDF Apr-08 Data sheet ( Hoja de datos )

Número de pieza Apr-08
Descripción Voice Recording & Playback Device Voice Recording & Playback Device
Fabricantes Apuls Intergrated Circuits 
Logotipo Apuls Intergrated Circuits Logotipo



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INTEGRATED CIRCUITS INC.
APR6008
Voice Recording & Playback Device
8 Minute Duration
Features
• Multi-level analog storage
• Single 3V power supply
- High quality audio recording and playback
• Low power consumption
• Dual mode storage of analog and/or digital data
- Eliminates the need for separate digital memory
• Advanced, non-volatile Flash memory technology
- Playback operating current: 15 mA typical
- Standby current: 1 u A maximum
- Automatic power-down
- No battery backup required
• Multiple package options available
• SPI interface
- Allows any commercial microcontroller to control
the device
• Programmable Sampling Clock
- Allows user to choose quality and duration levels
- CSP, SOP, PDIP, Bare Die
• On-board clock prescaler
- Eliminates the need for external clock dividers
• Automatic squelch circuit
- Reduces background noise during quiet passages
General Description
The APR6008 offers non-volatile storage of voice and/or data
in advanced Multi-Level Flash memory. Up to 8 minutes of
audio recording and playback can be accommodated. A max-
imum of 30K bits of digital data can be stored. APR6008
devices can be cascaded for longer duration recording or
greater digital storage. Device control is accomplished
through an industry standard SPI interface that allows a
microcontroller to manage message recording and playback.
This flexible arrangement allows for the widest variety of
messaging options. The APR6008 is ideal for use in cellular
and cordless phones, telephone answering devices, personal
digital assistants, personal voice recorders, and voice pag-
ers.
APLUS Integrated achieves this high level of storage capabi-
lity by using a proprietary analog multi-level storage te chnol -
logyi mplemented in an advanced non-volatile Flash memory
process. Each memory cell can typically store 256 voltage
levels. This allows the APR6008 voice to reproduce audio
signals in their natural form, eliminating the need for enco-
ding and compression which can introduce distortion.
Figure 1 APR6008 Pinout Diagrams
/C S
DI
DO
VSSD
NC
NC
NC
ANAOUT-
AN AO U T+
NC
/R E S E T
VSSA
AUDOUT
SQLCAP
28 pin DIP
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
SCLK
VCCD
EXTCLK
/IN T
SAC
VSSA
NC
/B U S Y
NC
NC
VCCA
AN A IN +
AN A IN -
/SQ LO UT
2002/5/10
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Apr-08 pdf
APR6008
Table 1 Sequential Command Timing
Current Command
NOP
SID
PWRUP
Any Command
Any Command
Next command
Timing Symbol
Tnext1 5u SEC
Tnext2 5m SEC
STOP_PWDN
SET_REC
REC
SET_PLAY
PLAY
SET_FWD
FWD
DIG_WRITE
DIG_READ
DIG_ERASE
STOP
PWRUP
STOP, STOP_PWDN, SET_REC, REC,NOP
Tnext2 5m SEC
Within SAC Low Time
STOP, STOP_PWDN, SET_FWD, FWD, SET_PLAY,PLAY, NOP
SET_FWD, FWD, STOP, STOP_PWDN
Any Digital Command, STOP, STOP_PWDN
Note: For partial DIG_READ Tnext2 is measured from the extra clock low that follows the
rise of /CS, not from the rise of /CS
Any Command
Tnext3
8K sampling rate: 376m SEC
4K sampling rate: 752 m SEC
Tnext4 470m SEC
OpCode Command Description
Designers have access to a total of 14 OpCodes. These
OpCodes are listed in Table 2. The name of the Opcode
appears in the left hand column. The following two columns
represent the actual binary information contained in the 20 bit
data stream. Some commands have limits on which com-
mand can follow them. These limits are shown in the “Allow-
able Follow on Commands” column. The last column
summarizes each command.
Combinations of OpCodes can be used to accommodate
almost any memory management scheme.
Table 2 APR6008 Operational Codes
Instruction OpCode
Name
(5 bits)
Opcode Parameters (15bits)
NOP
SID
SET_FWD
[Op4 - Op0]
[00000]
[00001]
[00010]
[Address MSB - Address LSB]
[Address 14 - Address 0]
[Don’t Care]
[Don’t care]
Sector Address
[A14 - A0]
FWD
[00011]
[Don’t care]
PWRUP
[00100]
STOP
STOP_PWDN
[00110]
[00111]
[A14-A10]: all zeros
[A9-A2]: EXTCLK divider ratio
[A1-A0]: Sample Rate Frequency
[Don’t care]
[Don’t care]
Allowable Follow
on Commands
Summary
All Commands
All Commands
SET_FWD,
FWD, STOP,
STOP_PWDN
SET_FWD,
FWD, STOP,
STOP_PWDN
All Commands
All Commands
PWRUP
No Operation
Causes the silicon ID to be read.
Starts a fast forward operation from the
sector address specified.
Starts a fast forward operation from the
current sector address.
Resets the device to initial conditions.
Sets the sample frequency and divider
ratios.
Stops the current operation.
Stops the current operation. Causes the
device to enter power down mode.
Voice Recording & Playback Device
Revision 2.1
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5 Page





Apr-08 arduino
APR6008
Reading Digital Data
Digital data is read from the device using the DIG_READ
command. To read data you must send a DIG_READ com-
mand immediately followed by 3012 don’t care bits during the
same /CS cycle. The data previously stored in the specified
sector will begin to appear on the DO pin after the current
device status or SID and four buffer bits. The next 3004 bits
are the previously stored data. The first bit shifted out is the
first bit that was written. The last bit shifted out is the last bit
that was written. There are four random don’t care bits follow-
ing the 3004 bits of user data.
An incomplete read of the sector is allowed. An incomplete
read is defined a a read with less than 3032 clock cycles. All
incomplete read cycles require one extra SCLK cycle after
the /CS signal returns high.
Figure 12 shows a timing diagram which describes the entire
process for a complete sector read. All timing with the excep-
tion of TpSCLK should adhere to the specifications given in
Figure 4 and Figure 7. The TpSCLK specification is replaced
by the DTpSCLK when reading digital data.
Figure 12 Reading Digital Data
SCLK
/C S
Total 3032 clock cycles
D I DIG_READ COMMAND
3012 don’t Care Bits
DO
SID or CDS
X XX X
3004 bits of previously stored data
X XXX
Voice Recording & Playback Device
Revision 2.1
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