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PCM56P-K Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer PCM56P-K
Beschreibung Serial Input 16-Bit Monolithic DIGITAL-TO-ANALOG CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 9 Seiten
PCM56P-K Datasheet, Funktion
® PCM56P
PCM56U
DESIGNED FOR AUDIO
Serial Input 16-Bit Monolithic
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q SERIAL INPUT
q –92dB MAX THD: FS Input, K Grade
q –74dB MAX THD: –20dB Input, K Grade
q 96dB DYNAMIC RANGE
q NO EXTERNAL COMPONENTS REQUIRED
q 16-BIT RESOLUTION
q 15-BIT MONOTONICITY, TYP
q 0.001% OF FSR TYP DIFFERENTIAL
LINEARITY ERROR
q 1.5µs SETTLING TIME, TYP: Voltage Out
q ±3V OR ±1mA AUDIO OUTPUT
q EIAJ STC-007-COMPATIBLE
q OPERATES ON ±5V TO ±12V SUPPLIES
q PINOUT ALLOWS IOUT OPTION
q PLASTIC DIP OR SOIC PACKAGE
DESCRIPTION
The PCM56 is a state-of-the-art, fully monotonic,
digital-to-analog converter that is designed and
specified for digital audio applications. This device
employs ultra-stable nichrome (NiCr) thin-film
resistors to provide monotonicity, low distortion, and
low differential linearity error (especially around
bipolar zero) over long periods of time and over the
full operating temperature.
This converter is completely self-contained with a
stable, low noise, internal zener voltage reference;
high speed current switches; a resistor ladder net-
work; and a fast settling, low noise output operational
amplifier all on a single monolithic chip. The
converters are operated using two power supplies that
can range from ±5V to ±12V. Power dissipation with
±5V supplies is typically less than 200mW. Also
included is a provision for external adjustment of the
MSB error (differential linearity error at bipolar zero)
to further improve total harmonic distortion (THD)
specifications if desired. Few external components
are necessary for operation, and all critical
specifications are 100% tested. This helps assure the
user of high system reliability and outstanding overall
system performance.
The PCM56 is packaged in a high-quality 16-pin
molded plastic DIP package or SOIC and has passed
operating life tests under simultaneous high-pressure,
high-temperature, and high-humidity conditions.
Reference
16-Bit
IOUT DAC
16-Bit Input Latch
RF
Audio
Output
16-Bit Serial-to-Parallel Conversion
Clock LE Data
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
©1987 Burr-Brown Corporation
PDS-700D
Printed in U.S.A. August, 1993






PCM56P-K Datasheet, Funktion
A much simpler method is to dynamically adjust the DLE at
0.1 BPZ. Again, refer to Figure 6 for circuitry and component
values. Assuming the device has been installed in a digital
audio application circuit, send the appropriate digital input
to produce a –80dB level sinusoidal output. While measuring
the THD of the audio circuit output, adjust the 100k
0.01
(–20dB)
potentiometer until a minimum level of distortion is observed.
0.001
100 1k
Frequency (Hz)
(Full Scale)
10k 20k
FIGURE 5. Total Harmonic Distortion (THD) vs Frequency.
INSTALLATION AND
OPERATING INSTRUCTIONS
POWER SUPPLY CONNECTIONS
For optimum performance and noise rejection, power supply
decoupling capacitors should be added as shown in the
Connection Diagram. These capacitors (1µF tantalum or
electrolytic recommended) should be located close to the
converter.
MSB ERROR ADJUSTMENT PROCEDURE
(OPTIONAL)
The MSB error of the PCM56 can be adjusted to make the
differential linearity error (DLE) at BPZ essentially zero.
This is important when the signal output levels are very low,
because zero crossing noise (DLE at BPZ) becomes very
significant when compared to the small code changes
occurring in the LSB portion of the converter.
Differential linearity error at bipolar zero and THD are
guaranteed to meet data sheet specifications without any
external adjustment. However, a provision has been made
for an optional adjustment of the MSB linearity point which
makes it possible to eliminate DLE error at BPZ. Two
procedures are given to allow either static or dynamic
adjustment. The dynamic procedure is preferred because of
the difficulty associated with the static method (accurately
measuring 16-bit LSB steps).
To statically adjust DLE at BPZ, refer to the circuit shown
in Figure 6, or the PCM56 connection diagram.
After allowing ample warm-up time (5-10 minutes) to assure
stable operation of the PCM56, select input code FFFF
hexadecimal (all bits on except the MSB). Measure the
audio output voltage using a 6-1/2 digit voltmeter and record
it. Change the digital input code to 0000 hexadecimal (all
bits off except the MSB). Adjust the 100kpotentiometer to
make the audio output read 92µV more than the voltage
reading of the previous code (a 1LSB step = 92µV).
Trim 15
470k
100k200k
1 –VS
MSB Adjust 14
FIGURE 6. MSB Adjustment Circuit.
INPUT TIMING CONSIDERATIONS
Figure 7 and 8 refer to the input timing required to interface
the inputs of PCM56 to a serial input data stream. Serial data
is accepted in Binary Two’s Complement (BTC) with the
MSB being loaded first. Data is clocked in on positive going
clock (CLK) edges and is latched into the DAC input
register on negative going latch enable (LE) edges.
The latch enable input must be high for at least one clock
cycle before going low, and then must be held low for at
least one clock cycle. The last 16 data bits clocked into the
serial input register are the ones that are transferred to the
DAC input register when latch enable goes low. In other
words, when more than 16 clock cycles occur between a
latch enable, only the data present during the last 16 clocks
will be transferred to the DAC input register.
One requirement for clocking in all 16 bits is the necessity
for a “17th” clock pulse. This automatically occurs when the
clock is continuous (last bit shifts in on the first bit of the
next data word). If the clock is stopped between input of 16-
bit data words, the latch enable (LE) must remain low until
after the first clock of the next 16-bit data word stream. This
ensures that the latch is properly set up.
Figure 7 refers to the general input format required for the
PCM56. Figure 8 shows the specific relationships between
the various signals and their timing constraints.
INSTALLATION
CONSIDERATIONS
If the optional external MSB error circuitry is used, a
potentiometer with adequate resolution and a TCR of 100ppm/
°C or less is required. Also, extra care must be taken to
insure that no leakage path (either AC or DC) exists to pin
14. If the circuit is not used, pins 14 and 15 should be left
open.
The PCM converter and the wiring to its connectors should
be located to provide the optimum isolation from sources of
RFI and EMI. The important consideration in the elimination
®
PCM56
6

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