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PCM3000E Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer PCM3000E
Beschreibung Stereo Audio CODEC 18-BITS/ SERIAL INTERFACE TM
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 21 Seiten
PCM3000E Datasheet, Funktion
® F49PP%OCM3001E
PCM3000E
PCM3000
PCM3001
For most current data sheet and other product
information, visit www.burr-brown.com
Stereo Audio CODEC
TM
18-BITS, SERIAL INTERFACE
FEATURES
q MONOLITHIC 18-BIT ∆Σ ADC AND DAC
q 16- OR 18-BIT INPUT/OUTPUT DATA
q STEREO ADC:
Single-ended Voltage Input
64X Oversampling
High Performance:
–88dB THD+N
94dB SNR
94dB Dynamic Range
Digital High-Pass Filter
q STEREO DAC:
Single-ended Voltage Output
Analog Low Pass Filter
64X Oversampling
High Performance:
–90dB THD+N
98dB SNR
97dB Dynamic Range
q SPECIAL FEATURES (PCM3000):
Digital De-emphasis
Digital Attenuation (256 Steps)
Soft Mute
Analog Loop Back
q SAMPLE RATE: Up to 48kHz
q SYSTEM CLOCK: 256fS, 384fS, 512fS
q SINGLE +5V POWER SUPPLY
q SMALL PACKAGE: SSOP-28
DESCRIPTION
The PCM3000/3001 is a low cost single chip stereo
audio CODEC (analog-to-digital and digital-to-analog
converter) with single-ended analog voltage input and
output.
Both ADCs and DACs employ delta-sigma modula-
tion with 64X oversampling. The ADCs include a
digital decimation filter and the DACs include an 8X
oversampling digital interpolation filter. The DACs
also include digital attenuation, de-emphasis, infinite
zero detection and soft mute to form a complete
subsystem. The PCM3000/3001 operates with left-
justified, right-justified, I2S or DSP data formats.
PCM3000 can be programmed with a 3-wire serial
interface for special features and data formats.
PCM3001 can be pin-programmed for data formats.
Fabricated on a highly advanced CMOS process, the
PCM3000/3001 is suitable for a wide variety of cost-
sensitive consumer applications where good perfor-
mance is required. Applications include sampling key-
boards, digital mixers, mini-disc recorders, hard-disk
recorders, karaoke systems, DSP-based car stereo,
DAT recorders, and video conferencing.
Lch In
Rch In
Analog Front-End
Lch Out
Rch Out
Low Pass Filter
and
Output Buffer
Delta-Sigma
Modulator
Multi-Level
Delta-Sigma
Modulator
Digital
Decimation
Filter
Digital
Interpolation
Filter
Serial Interface
and
Mode Control
Digital Out
Digital In
Mode Control
System Clock
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1996 Burr-Brown Corporation
PDS-1342E
1
PCM3P0rin0te0d /in3U0.S0.A1., January, 2000
®






PCM3000E Datasheet, Funktion
TYPICAL PERFORMANCE CURVES
DAC SECTION
At TA = +25°C, VCC = VDD = +5V, fIN = 1.0kHz, fS = 44.1kHz, 18-bit data, and SYSCLK = 384fS, unless otherwise noted.
THD+N vs TEMPERATURE
THD+N vs POWER SUPPLY
0.01 4.0 0.01
0.008
0.006
–60dB
3.0 0.008
2.0 0.006
–60dB
0.004
0.002
–25
1.0
0dB
0
0 25 50 75 85 100
Temperature (°C)
0.004
0.002
0dB
4.5 4.75 5.0 5.25 5.5
VCC (V)
4.0
3.0
2.0
1.0
0
SNR and DYNAMIC RANGE vs POWER SUPPLY
100 100
Dynamic Range
98 98
96
SNR
96
94 94
92 92
4.5 4.75 5.0 5.25 5.50
VCC (V)
THD+N vs SYSTEM CLOCK
and SAMPLING FREQUENCY
0.01
0.008
0.006
0.004
0.002
48kHz
–60dB
48kHz
0dB
44.1kHz
44.1kHz
256fS
384fS
System Clock
512fS
4.0
3.0
2.0
1.0
0
0.01
0.008
0.006
0.004
0.002
THD+N vs INPUT DATA RESOLUTION
–60dB
0dB
16-Bit
18-Bit
Resolution
4.0
3.0
2.0
1.0
0
®
PCM3000/3001
6

6 Page









PCM3000E pdf, datenblatt
LRCIN
BCKIN
DIN
tLRP
tBL tLB
tBCH
tBCL
tBCY
tDIS tDIH
DOUT
tBDO
1.4V
1.4V
1.4V
tLDO
0.5 x VDD
BCKIN Pulse Cycle Time
BCKIN Pulse Width High
BCKIN Pulse Width Low
BCKIN Rising Edge to LRCIN Edge
LRCIN Edge to BCKIN Rising Edge
LRCIN Pulse Width
DIN Set-up Time
DIN Hold Time
DOUT Delay Time to BCKIN Falling Edge
DOUT Delay Time to LRCIN Edge
Rising Time of All Signals
Falling Time of All Signals
tBCY
tBCH
tBCL
tBL
tLB
tLRP
tDIS
tDIH
tBDO
tLDO
tRISE
tFALL
300ns (min)
120ns (min)
120ns (min)
40ns (min)
40ns (min)
tBCY (min)
40ns (min)
40ns (min)
40ns (max)
40ns (max)
20ns (max)
20ns (max)
FIGURE 4. Audio Data Input/Output Timing.
SYSTEM CLOCK
The system clock for the PCM3000/3001 must be either 256fS,
384fS or 512fS, where fS is the audio sampling frequency. The
system clock can be either a crystal oscillator placed between
XTI (Pin 20) and XTO (Pin 21), or an external clock input. If
an external clock is used, the clock is provided to either XTI
or CLKIO (Pin 22), and XTO is open. The PCM3000/3001
has an XTI clock detection circuit which senses if an XTI
clock is operating. When the external clock is delivered to
XTI, CLKIO is a buffered output of XTI. When XTI is
connected to ground, the external clock must be tied to
CLKIO. For best performance, the “External Clock Input 2”
circuit in Figure 5 is recommended.
The PCM3000/3001 also has a system clock detection circuit
which automatically senses if the system clock is operating at
256fS, 384fS, or 512fS. When a 384fS or 512fS system clock
is used, the clock is divided into 256fS automatically. The
256fS clock is used to operate the digital filters and the
modulators.
Table I lists the relationship of typical sampling frequencies
and system clock frequencies, and Figures 5 and 6 illustrate
the typical system clock connections and external system
clock timing.
SAMPLING RATE FREQUENCY
(kHz)
32
44.1
48
SYSTEM CLOCK FREQUENCY
(MHz)
256fS
8.1920
11.2896
12.2880
384fS
12.2880
16.9340
18.4320
512fS
16.3840
22.5792
24.5760
TABLE I. System Clock Frequencies.
®
PCM3000/3001
12

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