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PCM1754 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer PCM1754
Beschreibung 24-BIT/ 192 kHz SAMPLING ENHANCED MULTI-LEVEL/ DELTA-SIGMA/ AUDIO DIGITAL-TO-ANALOG CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 33 Seiten
PCM1754 Datasheet, Funktion
Burr-Brown Products
from Texas Instruments
PCM1753
PCM1754
PCM1755
SLES092A – OCTOBER 2003 – REVISED AUGUST 2004
24-BIT, 192 kHz SAMPLING ENHANCED MULTI-LEVEL, DELTA-SIGMA,
AUDIO DIGITAL-TO-ANALOG CONVERTER
FEATURES
D 24-Bit Resolution
D Analog Performance (VCC = 5 V):
Dynamic Range: 106 dB
SNR: 106 dB, Typical
THD+N: 0.002%, Typical
Full-Scale Output: 4 V p-p, Typical
D 4×/8× Oversampling Digital Filter:
Stop-Band Attenuation: –50 dB
Pass-Band Ripple: ±0.04 dB
D Sampling Frequency: 5 kHz to 200 kHz
D System Clock: 128 fS, 192 fS, 256 fS, 384 fS,
512 fS, 768 fS, 1152 fS With Auto Detect
D Software Control (PCM1753, PCM1755):
Accepts 16-, 18-, 20-, and 24-Bit Audio
Formats: Standard, I2S, and Left-Justified
Digital Attenuation: 0 dB to –63 dB,
0.5 dB/Step
Digital De-Emphasis
Digital Filter Rolloff: Sharp or Slow
Soft Mute
Zero Flags for Each Output
Open-Drain Output Zero Flag (PCM1755)
D Hardware Control (PCM1754):
I2S and 16-Bit Word, Right-Justified
44.1 kHz Digital De-Emphasis
Soft Mute
Zero Flag for L-, R-Channel Common
Output
D Power Supply: 5-V Single Supply
D Small 16-Lead SSOP Package, Lead-Free
APPLICATIONS
D A/V Receivers
D DVD Movie Players
D DVD Add-On Cards For High-End PCs
D DVD Audio Players
D HDTV Receivers
D Car Audio Systems
D Other Applications Requiring 24-Bit Audio
DESCRIPTION
The PCM1753/54/55 is a CMOS, monolithic, integrated
circuit, which includes stereo digital-to-analog converters
and support circuitry in a small 16-lead SSOP package.
The data converters use TI’s enhanced multilevel
delta-sigma architecture, which employs 4th-order noise
shaping and 8-level amplitude quantization to achieve
excellent dynamic performance and improved tolerance to
clock jitter. The PCM1753/54/55 accepts industry-
standard audio data formats with 16- to 24-bit data,
providing easy interfacing to audio DSP and decoder
chips. Sampling rates up to 200 kHz are supported. A full
set of user-programmable functions is accessible through
a three-wire serial control port, which supports register
write functions.
The PCM1753/55 is pin compatible with the PCM1748,
PCM1742, and PCM1741, except for pin 5.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
Audio Precision and System Two are trademarks of Audio Precision, Inc.
Other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright 2004, Texas Instruments Incorporated






PCM1754 Datasheet, Funktion
PCM1753
PCM1754
PCM1755
SLES092A – OCTOBER 2003 – REVISED AUGUST 2004
Terminal Functions
TERMINAL
NAME
NO.
PCM1753/PCM1755
I/O
DESCRIPTION
AGND
9 – Analog ground
BCK
1 I Audio data bit clock input
DATA
2 I Audio data digital input
DGND
4 – Digital ground
LRCK
MC
MD
ML
3 I L-channel and R-channel audio data latch enable input
14 I Mode control clock input(1)
13 I Mode control data input (1)
15 I Mode control latch input (1)
NC 5 –
SCK
16 I System clock input
VCC
VCOM
VOUTL
VOUTR
ZEROR/ZEROA
ZEROL/NA
PCM1754
6
10
7
8
11
12
– Analog power supply, 5 V
– Common voltage decoupling
O Analog output for L-channel
O Analog output for R-channel
O Zero flag output for R-channel/Zero flag output for L-/R-channels (2)
O Zero flag output for L-channel/Not assigned (2)
AGND
9 – Analog ground
BCK
1 I Audio-data bit-clock input
DATA
DEMP
2 I Audio-data digital input
13 I De-emphasis control (1)
DGND
FMT
4 – Digital ground
15 I Data format select (1)
LRCK
MUTE
3 I L-channel and R-channel audio data latch enable input
14 I Analog mixing control (1)
NC 5 –
SCK
TEST
16 I System clock input
12 I Test pin. Ground or open (1)
VCC 6 – Analog power supply, 5 V
VCOM
10 – Common voltage decoupling
VOUTL
7 O Analog output for L-channel
VOUTR
8 O Analog output for R-channel
ZEROA
11 O Zero flag output for L/R channels
(1) Schmitt-trigger input with internal pulldown.
(2) Open-drain output (PCM1755).
www.ti.com
6

6 Page









PCM1754 pdf, datenblatt
PCM1753
PCM1754
PCM1755
SLES092A – OCTOBER 2003 – REVISED AUGUST 2004
SYSTEM CLOCK AND RESET FUNCTIONS
www.ti.com
System Clock Input
The PCM1753/54/55 requires a system clock for operating the digital interpolation filters and multilevel
delta-sigma modulators. The system clock is applied at the SCK input (pin 16). Table 1 shows examples of
system clock frequencies for common audio sampling rates.
Figure 19 shows the timing requirements for the system clock input. For optimal performance, it is important
to use a clock source with low phase-jitter and noise. TI’s PLL170x family of multiclock generators is an excellent
choice for providing the PCM1753/54/55 system clock.
Table 1. System Clock Rates for Common Audio Sampling Frequencies
SAMPLING FREQUENCY
8 kHz
128 fS
1.0240
SYSTEM CLOCK FREQUENCY (fSCLK) (MHz)
192 fS
256 fS
384 fS
512 fS
768 fS
1.5360
2.0480
3.0720
4.0960
6.1440
16 kHz
2.0480
3.0720
4.0960
6.1440
8.1920
12.2880
32 kHz
4.0960
6.1440
8.1920
12.2880
16.3840
24.5760
44.1 kHz
5.6448
8.4672
11.2896
16.9344
22.5792
33.8688
48 kHz
6.1440
9.2160
12.2880
18.4320
24.5760
36.8640
88.2 kHz
11.2896
16.9344
22.5792
33.8688
45.1584
(1)
96 kHz
12.2880
18.4320
24.5760
36.8640
49.1520
(1)
192 kHz
24.5760
36.8640
49.1520
(1)
(1)
(1)
(1) This system clock rate is not supported for the given sampling frequency.
1152 fS
9.2160
18.4320
36.8640
(1)
(1)
(1)
(1)
(1)
System Clock (SCK)
H
L
t(SCKH)
t(SCKL)
t(SCY)
2.0 V
0.8 V
PARAMETERS
SYMBOL MIN TYP MAX UNITS
System clock pulse duration, high
t(SCKH)
7
System clock pulse duration, low
System clock pulse cycle time
(1) 1/128 fS, 1/256 fS, 1/384 fS, 1/512 fS, 1/768 fS, or 1/1152 fS
t(SCKL)
7
t(SCY)
(1)
Figure 19. System Clock Input Timing
ns
ns
ns
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