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PCM1728 Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer PCM1728
Beschreibung 24-Bit/ 96kHz Sampling CMOS Delta-Sigma Stereo Audio DIGITAL-TO-ANALOG CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 11 Seiten
PCM1728 Datasheet, Funktion
®
49%PCM1728
FPO
PCM1728
TM 24-Bit, 96kHz Sampling
CMOS Delta-Sigma Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q ENHANCED MULTI-LEVEL DELTA-SIGMA DAC
q SAMPLING FREQUENCY (fS): 16kHz - 96kHz
q INPUT AUDIO DATA WORD:
16-, 20-, 24-Bit
q HIGH PERFORMANCE:
THD+N: –96dB
Dynamic Range: 106dB
SNR: 106dB
Analog Output Range: 0.62 x VCC (Vp-p)
q 8x OVERSAMPLING DIGITAL FILTER:
Stop Band Attenuation: –82dB
Passband Ripple: ±0.002dB
q MULTI FUNCTIONS:
Digital De-emphasis
Soft Mute
Zero Flag
q +5V SINGLE SUPPLY OPERATION
q SMALL 28-LEAD SSOP PACKAGE
DESCRIPTION
The PCM1728 is designed for mid- to high-grade
digital audio applications which achieve 96kHz sam-
pling rates with 24-bit audio data. PCM1728 uses a
newly developed, enhanced multi-level delta-sigma
modulator architecture that improves audio dynamic
performance and reduces jitter sensitivity in actual
applications. The internal digital filter operates at 8X
oversampling at a 96kHz sampling rate.
The PCM1728 has superior audio dynamic perfor-
mance, 24-bit resolution, and 96kHz sampling, mak-
ing it ideal for mid- to high-grade audio applications
such as CD, DVD, and musical instruments.
BCKIN
LRCIN
DIN
I2S
DM1
DM0
IW0
IW1
MUTE
RST
Serial
Input
I/F
Mode
Control
I/F
8X Oversampling
Digital Filter with
Function
Controller
Enhanced
Multi-level
Delta-Sigma
Modulator
DAC
DAC
Low-pass
Filter
Low-pass
Filter
SCK
Crystal/OSC
Open Drain
Power Supply
VOUTL
EXTL
VOUTR
EXTR
ZERO
XTI XTO
CLKO VCC1 AGND1 VDD DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111 • Twx: 910-952-1111
Internet: http://www.burr-brown.com/ • FAXLine: (800) 548-6133 (US/Canada Only) • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1998 Burr-Brown Corporation
PDS-1453A
Printed in U.S.A. April, 1998






PCM1728 Datasheet, Funktion
SYSTEM CLOCK
The system clock for PCM1728 must be either 256fS, 384fS,
512fS or 768fS, where fS is the audio sampling frequency
(typically 32kHz, 44.1kHz, 48kHz, or 96kHz). But 768fS at
96kHz is not accepted.
The system clock can be either a crystal oscillator placed
between XTI (pin 5) and XTO (pin 6), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.
PCM1728 has a system clock detection circuit which auto-
matically senses if the system clock is operating at 256fS ~
768fS. The system clock should be synchronized with LRCIN
(pin 1) clock. LRCIN (left-right clock) operates at the sam-
pling frequency fS. In the event these clocks are not synchro-
nized, PCM1728 can compensate for the phase difference
internally. If the phase difference between left-right and
system clocks is greater than 6-bit clocks (BCKIN), the
synchronization is performed internally. While the synchro-
nization is processing, the analog output is forced to a DC
level at bipolar zero. The synchronization typically occurs in
less than 1 cycle of LRCIN.
Externl Clock Input
System Clock
(256/384/
512/768fS)
4 CLKO
5 XTI
6 XTO
PCM1728
Crystal Resonator Oscillation
System Clock
Buffer Out
Buffer
4 CLKO
5 XTI
C1
C2 XTAL
C1 C2 : 10pF ~ 30pF
6 XTO
PCM1728
FIGURE 1. System Clock Connection.
Typical input system clock frequencies to the PCM1728 are
shown in Table I, also, external input clock timing require-
ments are shown in Figure 2.
“H”
XTI
tSCKH
“L”
tSCKL
System Clock Pulse Width High tSCKIH : 7ns MIN
System Clock Pulse Width Low tSCKIL : 7ns MIN
2.0V
0.8V
FIGURE 2. XTI Clock Timing.
DATA INTERFACE FORMATS
Digital audio data is interfaced to PCM1728 on pins 1, 2,
and 3, LRCIN (left-right clock), DIN (data input) and
BCKIN (bit clock). PCM1728 can accept both standard, I2S,
and left justified data formats.
Figure 3 illustrates acceptable input data formats. Figure 4
shows required timing specification for digital audio data.
Reset
PCM1728 has both internal power-on reset circuit and the
RST pin (pin 22), which accepts an external forced reset by
RST = LOW. For internal power on reset, initialization is
done automatically at power on VDD >2.2V (typ). During
internal reset = LOW, the output of the DAC is invalid and
the analog outputs are forced to VCC /2. Figure 5 illustrates
the timing of the internal power on reset.
PCM1728 accepts an external forced reset when RST = LOW.
When RST = LOW, the output of the DAC is invalid and the
analog outputs are forced to VCC/2 after internal initialization
(1024 system clocks count after RST = HIGH.) Figure 6
illustrates the timing of the RST pin.
Zero Out (pin 21)
If the input data is continuously zero for 65536 cycles of
BCK, an internal FET is switched to “ON”. The drain of the
internal FET is the zero-pin, it will enable “wired-or” with
external circuit.
SAMPLING RATE FREQUENCY (fS) - LRCIN
32kHz
44.1kHz
48kHz
96kHz
256fS
8.1920
11.2896
12.2880
24.5760
NOTE: (1) The internal crystal oscillator frequency cannot be larger than 24.576MHz.
TABLE I. Typical System Clock Frequency.
®
PCM1728
6
SYSTEM CLOCK FREQUENCY - MHz
384fS
12.2880
16.9340
18.4320
36.8640(1)
512fS
16.3840
22.5792
24.5760
49.1520(1)
768fS
24.5760
33.8688(1)
36.8640(1)

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