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PCM1717E Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer PCM1717E
Beschreibung Stereo Audio DIGITAL-TO-ANALOG CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 14 Seiten
PCM1717E Datasheet, Funktion
®
PCMF4197P1%O7 ®
PCM1717
For most current data sheet and other product
information, visit www.burr-brown.com
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q ACCEPTS 16- OR 18-BIT INPUT DATA
q COMPLETE STEREO DAC:
8X Oversampling Digital Filter
Multi-Level Delta-Sigma DAC
Analog Low Pass Filter
Output Amplifier
q HIGH PERFORMANCE:
–90dB THD+N
96dB Dynamic Range
100dB SNR
q SYSTEM CLOCK: 256fs or 384fs
q WIDE POWER SUPPLY: +2.7V to +5.5V
q SELECTABLE FUNCTIONS:
Soft Mute
Digital Attenuation (256 Steps)
Digital De-emphasis
Output Mode: L, R, Mono, Mute
q SMALL SSOP-20 PACKAGE
DESCRIPTION
The PCM1717 is a complete low cost stereo, audio
digital-to-analog converter, including digital interpo-
lation filter, 3rd-order delta-sigma DAC, and analog
output amplifiers. PCM1717 is fabricated on a highly
advanced 0.6µ CMOS process. PCM1717 accepts
16- or 18-bit normal input data format, or 16- or
18-bit I2S data format.
The digital filter performs an 8X interpolation func-
tion, as well as special functions such as soft mute,
digital attenuation, and digital de-emphasis. The digi-
tal filter features –35dB stop band attenuation and
±0.17dB ripple in the pass band.
PCM1717 is suitable for a wide variety of cost-sensitive
consumer applications where good performance is re-
quired. Its low cost, small size, and single +5V power
supply make it ideal for automotive CD players, book-
shelf CD players, BS tuners, keyboards, MPEG audio,
MIDI applications, set-top boxes, CD-ROM drives,
CD-Interactive, and CD-Karaoke systems.
BCKIN
LRCIN
DIN
ML/MUTE
MC/DM0
MD/DM1
MODE
RSTB
Serial
Input
I/F
Mode
Control
I/F
Reset
8X Oversampling
Digital Filter with
Multi Function
Control
Multi-level
Delta-Sigma
Modulator
DAC
Multi-level
Delta-Sigma
Modulator
DAC
Output Amp
and
Low-pass
Filter
Output Amp
and
Low-pass
Filter
BPZ-Cont.
Clock/OSC Manager
Open Drain
Power Supply
VOUTL
D/C_L
VOUTR
D/C_R
ZERO
XTI XTO CLKO
VCC AGND VDD DGND
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1995 Burr-Brown Corporation
PD1S-1289D
PCPrinMted1in7U1.S7.A. March, 2000
®






PCM1717E Datasheet, Funktion
SYSTEM CLOCK
The system clock for PCM1717 must be either 256fS or
384fS, where fS is the audio sampling frequency (typically
32kHz, 44.1kHz, or 48kHz). The system clock is used to
operate the digital filter and the modulator.
The system clock can be either a crystal oscillator placed
between XTI (pin 1) and XTO (pin 20), or an external clock
input to XTI. If an external system clock is used, XTO is
open (floating). Figure 1 illustrates the typical system clock
connections.
PCM1717 has a system clock detection circuit which auto-
matically senses if the system clock is operating at 256fS or
384fS. The system clock should be synchronized with LRCIN
(pin 4) clock. LRCIN (left-right clock) operates at the
sampling frequency fs. In the event these clocks are not
synchronized, PCM1717 can compensate for the phase dif-
ference internally. If the phase difference between left-right
and system clocks is greater than 6 bit clocks (BCKIN), the
synchronization is performed internally. While the synchro-
nization is processing, the analog output is forced to a DC
level at bipolar zero. The synchronization typically occurs in
less than 1 cycle of LRCIN.
DATA INTERFACE FORMATS
Digital audio data is interfaced to PCM1717 on pins 4, 5,
and 6—LRCIN (left-right clock), DIN (data input) and
BCKIN (bit clock). PCM1717 can accept both normal and
I2S data formats. Normal data format is MSB first, two’s
complement, right-justified. I2S data is compatible with
Philips serial data protocol. In the I2S format, the data is 16-
or 18-bit, selectable by bit 0 on Register 3 (Software Control
Mode). In the Hardware Mode, PCM1717 can only function
with 16-bit normal data. Figures 5 through 9 illustrate timing
and input formats.
CLKO
CLKO
Internal System Clock
Internal System Clock
C1
X’tal
XTI
External Clock
XTI
C2
XTO
C1, C2 = 10 to 20pF
PCM1717E
CRYSTAL RESONATOR CONNECTION
FIGURE 1. Internal Clock Circuit Diagram and Oscillator Connection.
XTO
PCM1717E
EXTERNAL CLOCK INPUT
XTO pin = No Connection
tXTIH
1/256fS or 1/384fS
tXTIL
External System Clock High
External System Clock Low
FIGURE 2. External Clock Timing Requirements.
tXTIH
tXTIL
64% OF VDD
28% OF VDD
10ns (min)
10ns (min)
®
PCM1717
6

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PCM1717E pdf, datenblatt
POWER SUPPLY
CONNECTIONS
PCM1717 has two power supply connections: digital (VDD)
and analog (VCC). Each connection also has a separate
ground. If the power supplies turn on at different times, there
is a possibility of a latch-up condition. To avoid this condi-
tion, it is recommended to have a common connection
between the digital and analog power supplies. If separate
supplies are used without a common connection, the delta
between the two supplies during ramp-up time must be less
than 0.6V.
An application circuit to avoid a latch-up condition is shown
in Figure 11.
A block diagram of the 5-level delta-sigma modulator is
shown in Figure 12. This 5-level delta-sigma modulator has
the advantage of stability and clock jitter sensitivity over the
typical one-bit (2 level) delta-sigma modulator.
The combined oversampling rate of the delta-sigma modu-
lator and the internal 8-times interpolation filter is 48fS for
a 384fS system clock, and 64fS for a 256fS system clock. The
theoretical quantization noise performance of the 5-level
delta-sigma modulator is shown in Figure 13.
Digital
Power Supply
Analog
Power Supply
VDD
DGND
VCC
AGND
FIGURE 11. Latch-up Prevention Circuit.
BYPASSING POWER SUPPLIES
The power supplies should be bypassed as close as possible
to the unit. Refer to Figure 10 for optimal values of bypass
capacitors.
THEORY OF OPERATION
The delta-sigma section of PCM1717 is based on a 5-level
amplitude quantizer and a 3rd-order noise shaper. This
section converts the oversampled input data to 5-level delta-
sigma format.
20
0
–20
–40
–60
–80
–100
–120
–140
–160
0
3rd-ORDER ∆Σ MODULATOR
5 10 15 20
Frequency (kHz)
FIGURE 13. Quantization Noise Spectrum.
25
In
8fS
18-Bit
+
+
Z–1
+
+
Z–1
+
+
Z–1
Out
48fS (384fS)
64fS (256fS)
FIGURE 12. 5-Level ∆Σ Modulator Block Diagram.
®
PCM1717
+
++
5-level Quantizer
4
3
2
1
0
12

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