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PCM1710U Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer PCM1710U
Beschreibung Stereo Audio DIGITAL-TO-ANALOG CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 17 Seiten
PCM1710U Datasheet, Funktion
® 49%
FPO
PCM1710U
Stereo Audio
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q COMPLETE STEREO DAC:
8X Oversampling Digital Filter
Multi-Level Delta-Sigma DAC
Analog Low Pass Filter
Output Amplifier
q HIGH PERFORMANCE:
–92dB THD+N
98dB Dynamic Range
110dB SNR
q ACCEPTS 16 OR 20 BITS INPUT DATA
q SYSTEM CLOCK: 256fs or 384fs
q SINGLE +5V POWER SUPPLY
q ON-CHIP DIGITAL FILTER:
Soft Mute and Attenuator
Digital De-emphasis
Double-Speed Dubbing Mode
q SMALL 28-PIN SOIC PACKAGE
DESCRIPTION
The PCM1710 is a complete stereo audio digital-to-
analog converter, including digital interpolation filter,
delta-sigma DAC, and analog voltage output. PCM1710
can accept either 16-bit normal or 20-Bit normal input
data (MSB first, right justified), or 16-bit IIS data
(32-bits per word, continuous clock).
The digital filter performs an 8X interpolation func-
tion, as well as special functions such as soft mute,
digital attenuation, de-emphasis and double-speed
dubbing. Performance of the digital feature is excel-
lent, featuring –62dB stop band attenuation and
±0.008dB ripple in the pass band.
PCM1710 is suitable for a wide variety of consumer
applications where good performance is required.
Its low cost, small size and single +5V power supply
make it ideal for automotive CD players, bookshelf
CD players, BS tuners, keyboards, MPEG audio,
MIDI applications, set-top boxes, CD-ROM drives,
CD-Interactive and CD-Karaoke systems.
Digital In
Input Interface
and
Attentuator
Mode Control
Oversampling
Digital Filter
System Clock
4th-Order
Multi-Level
Delta
Sigma
DAC
Low-Pass
Filter
Output
Op Amp
Lch OUT
Rch OUT
International Airport Industrial Park • Mailing Address: PO Box 11400 • Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd. • Tucson, AZ 85706
Tel: (520) 746-1111 • Twx: 910-952-1111 • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1994 Burr-Brown Corporation
PDS-1217B
Printed in U.S.A. June, 1995






PCM1710U Datasheet, Funktion
BCKIN
DIN
LRCIN
FIGURE 4. Data Input Timing.
tBCWH
tBCY
tBCWL
tDH tDS
tBL tLB
MC
tMCWH
tMCWL
tMCY
MD
tMH tMS
tMCS
tMCH
ML
tMLY
MC, MD, ML
tF
FIGURE 5. Serial Mode Control Timing.
BCK Pulsewidth (H Level)
BCK Pulsewidth (L Level)
BCK Pulse Cycle Time
DIN Setup Time
DIN Hold Time
BCK Rising Edge ¨ LRCI Edge
LRC I Edge ¨ BCK Rising Edge
tBCWH
tBCWL
tBCY
tDS
tDH
tBL
tLB
70ns (min)
70ns (min)
140ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
TABLE I. Data Input Timing Specifications (Refer to
Figure 4).
tR
2.0V
0.8V
MC Pulsewidth (H Level)
MC Pulsewidth (L Level)
MC Pulse Cycle Time
MD Setup Time
MD Hold Time
ML Setup Time
ML Hold Time
ML Low-Level Time
MC, MD, ML Rise Time
MC, MD, ML Fall Time
tMCWH
tMCWL
tMCY
tMS
tMH
tMCS
tMCH
tMLY
tR
tF
50ns (min)
50ns (min)
100ns (min)
30ns (min)
30ns (min)
30ns (min)
30ns (min)
1/sysclk + 20ns (min)
15ns (max)
15ns (max)
TABLE II. Serial Mode Control Timing Specifications
(Refer to Figure 5).
®
PCM1710U
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PCM1710U pdf, datenblatt
Once the reset has been established on pin 27 (MC), the de-
emphasis frequency defaults to 44.1kHz. B5 is a master
control for de-emphasis. A high level on B5 enables de-
emphasis (frequency controlled by B3 and B4), and a low
level on B5 disables de-emphasis.
SOFT MUTE
Soft mute is enabled when B6 is high. The soft mute occurs
gradually, unlike the forced infinite zero detection. When
the mute data bit is high, complete muting will occur in
127/fs seconds. For fS = 44.1kHz, complete mute will occur
in 2.88ms.
DOUBLE-SPEED DUBBING
Double-speed dubbing is used when the application allows
for the CD to be copied at twice the normal playback rate.
Double-speed dubbing is enabled when B7 is high. This
mode can only operate when the system clock is set at 384fs.
Double-speed dubbing can only occur when the sample rate
is 44.1kHz. Since fS is set at 44.1kHz, the system clock in
double-speed mode is at 192fs.
MODE 2 CONTROLS
Mode 2 is enabled when B0 is high, B1 is low, and B2 is
high. This mode controls infinite zero detection, input reso-
lution, LRCI polarity and input format.
INFINITE ZERO DETECTION
B4 is used to enable or disable infinite zero detection.
PCM1710 monitors both data input (DIN) and bit clock
(BCKIN). When the data input is continuously zero or one
for 65,536 cycles of the bit clock, infinite zero detection
occurs, which forces the output of the PCM1710 to one-half
of VCC (typically 2.5V). Once this happens, only the output
amplifier is connected. This is done to avoid having the
noise shaped output spectrum of the DAC appear at the
output of the PCM1710. This function is especially useful
for CD applications when the player is between tracks. An
inherent attribute of all delta-sigma architectures is the
presence of quantization noise when the input is constant (all
1s or 0s). When the zero detect circuit disconnects the DAC
from the output amplifier, a very low level “click” noise may
be audible. The click noise occurs at approximately –76dB,
and in many cases is inaudible.
INPUT RESOLUTION
PCM1710 is capable of accepting either 16-bit or 20-bit
input data. Specifications for PCM1710 are tested and guar-
anteed using 16-bit data. When 20 bits are used, dynamic
performance is improved by approximately 2dB. Refer to
“Typical Performance Curves” for a comparison of 16-bit
and 20-bit data. A low on B5 places PCM1710 in 16-bit
mode, and a high on B5 sets PCM1710 to 20-bit mode.
SAMPLE RATE CLOCK POLARITY
B6 controls the polarity of the sample rate clock (LRCIN)
polarity. When B6 is low, data will be accepted on the left
channel when LRCIN is high, and on the right channel when
LRCIN is low. When B6 is high, data will be accepted on the
right channel when LRCIN is high, and on the left channel
when LRCIN is low.
INPUT FORMAT
Normal input mode for PCM1710 is MSB first, right justi-
fied. PCM1710 may also be operated with IIS (32 continu-
ous clock cycles per word) input format. When B7 is low,
the input format is “normal”. When B7 is high, the input
format is “IIS”. However, PCM1710 can only accept IIS
input format when it is in 16-bit mode. 20-bit data must be
entered in normal mode.
DEFAULT MODE
At initial power-on, default settings for PCM1710 are 44.1kHz
fS, de-emphasis off, mute off, double-speed off, infinite zero
detect on, 16-bit input LRCIN left channel high, and normal
input mode.
SYSTEM CLOCK
SAMPLING FREQUENCY
32kHz
32kHz
44.1kHz
44.1kHz
48kHz
48kHz
SYSTEM CLOCK FREQUENCY
256fs
384fs
256fs
384fs
256fs
384fs
8.1920MHz
12.2880MHz
11.2896MHz
16.9344MHz
12.2880MHz
18.4320MHz
TABLE VIII. Relationship of fs and System Clock.
NORMAL/DOUBLE-SPEED DUBBING
For most CD playback applications operating at 384fs, the
system clock frequency must be 16.9344MHz, in both the
normal mode and double-speed dubbing mode. Table VIII
illustrates the relationship between fs and output clock
frequency in both modes.
PARAMETER
XTI Input Clock Frequency
XTI Frequency
CLKO Output Clock Frequency
ML/DSD (PIN 28)
H
(Normal)
L
(Double Speed)
384fs
16.9344MHz
(fS = 44.1kHz)
384fs
192fs
16.9344MHz
(fS = 88.2kHz)
192fs
TABLE IX. Relationship Between Normal/Double Speed
and fs.
®
PCM1710U
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