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PCM1600Y Schematic ( PDF Datasheet ) - Burr-Brown Corporation

Teilenummer PCM1600Y
Beschreibung 24-Bit/ 96kHz Sampling/ 6-Channel/ Enhanced Multi-Level/ Delta-Sigma DIGITAL-TO-ANALOG CONVERTER
Hersteller Burr-Brown Corporation
Logo Burr-Brown Corporation Logo 




Gesamt 28 Seiten
PCM1600Y Datasheet, Funktion
® PCM1600
PCM1600
PCM1601
PCM1601
For most current data sheet and other product
information, visit www.burr-brown.com
TM 24-Bit, 96kHz Sampling, 6-Channel,
Enhanced Multi-Level, Delta-Sigma
DIGITAL-TO-ANALOG CONVERTER
FEATURES
q 24-BIT RESOLUTION
q ANALOG PERFORMANCE:
Dynamic Range: 105dB typ
SNR: 104dB typ
THD+N: 0.0018% typ
Full-Scale Output: 3.1Vp-p typ
q 8x OVERSAMPLING INTERPOLATION FILTER:
Stopband Attenuation: –82dB
Passband Ripple: ±0.002dB
q SAMPLING FREQUENCY: 10kHz to 100kHz
q ACCEPTS 16, 18, 20, AND 24-BIT AUDIO DATA
q DATA FORMATS: Standard, I2S, and Left-Justified
q SYSTEM CLOCK: 256fS, 384fS, 512fS, or 768fS
q USER-PROGRAMMABLE FUNCTIONS:
Digital Attenuation: 0dB to –63dB, 0.5dB/Step
Soft Mute
Zero Detect Mute
Zero Flags for Each Output Channel
Digital De-Emphasis
Digital Filter Roll-Off: Sharp or Slow
q DUAL SUPPLY OPERATION:
+5V Analog, +3.3V Digital
q 5V TOLERANT DIGITAL LOGIC INPUTS
q PACKAGES(1): LQFP-48 (PCM1600)
and MQFP-48 (PCM1601)
APPLICATIONS
q INTEGRATED A/V RECEIVERS
q DVD MOVIE AND AUDIO PLAYERS
q HDTV RECEIVERS
q CAR AUDIO SYSTEMS
q DVD ADD-ON CARDS FOR HIGH-END PCs
q DIGITAL AUDIO WORKSTATIONS
q OTHER MULTI-CHANNEL AUDIO SYSTEMS
DESCRIPTION
The PCM1600(1) and PCM1601(1) are CMOS mono-
lithic integrated circuits which feature six 24-bit audio
digital-to-analog converters and support circuitry in
either a LQFP-48 or MQFP-48 package. The digital-
to-analog converters utilize Burr-Brown’s enhanced
multi-level, delta-sigma architecture, which employ
4th-order noise shaping and 8-level amplitude quanti-
zation to achieve excellent signal-to-noise performance
and a high tolerance to clock jitter.
The PCM1600 and PCM1601 accept industry-stan-
dard audio data formats with 16- to 24-bit audio data.
Sampling rates up to 100kHz are supported. A full set
of user-programmable functions are accessible through
a 4-wire serial control port which supports register
write and readback functions.
NOTE: (1) The PCM1600 and PCM1601 utilize the same die and are
electrically the same. All references to the PCM1600 apply equally
to the PCM1601.
International Airport Industrial Park • Mailing Address: PO Box 11400, Tucson, AZ 85734 • Street Address: 6730 S. Tucson Blvd., Tucson, AZ 85706 • Tel: (520) 746-1111
Twx: 910-952-1111 • Internet: http://www.burr-brown.com/ • Cable: BBRCORP • Telex: 066-6491 • FAX: (520) 889-1510 • Immediate Product Info: (800) 548-6132
© 1999 Burr-Brown Corporation
PDS-1523C
Printed in U.S.A. March, 2000






PCM1600Y Datasheet, Funktion
TYPICAL PERFORMANCE CURVES
All specifications at +25°C, VCC = 5V, VDD = 3.3V, SYSCLK = 384fS (fS = 44.1kHz), and 24-bit input data, unless otherwise noted.
DIGITAL FILTER
Digital Filter (De-Emphasis Off, fS = 44.1kHz)
FREQUENCY RESPONSE
(Sharp Roll-Off)
0
–20
–40
–60
–80
–100
–120
–140
–160
0 0.5 1 1.5 2 2.5 3 3.5 4
Frequency (x fS)
FREQUENCY RESPONSE
(Slow Roll-Off)
0
–20
–40
–60
–80
–100
–120
–140
0
0.5 1.0
De-Emphasis Error
1.5 2.0 2.5
Frequency (x fS)
3.0 3.5
4.0
DE-EMPHASIS FREQUENCY RESPONSE (fS = 32kHz)
0
–2
–4
–6
–8
–10
0 2 4 6 8 10 12 14
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 44.1kHz)
0
–2
–4
–6
–8
–10
0 2 4 6 8 10 12 14 16 18 20
Frequency (kHz)
DE-EMPHASIS FREQUENCY RESPONSE (fS = 48kHz)
0
–2
–4
–6
–8
–10
0 2 4 6 8 10 12 14 16 18 20 22
Frequency (kHz)
®
PCM1600, PCM1601
0.003
0.002
0.001
0
–0.001
–0.002
–0.003
0
PASSBAND RIPPLE
(Sharp Roll-Off)
0.1 0.2
0.3 0.4
Frequency (x fS)
0.5
0
–2
–4
–6
–8
–10
–12
–14
–16
–18
–20
0
TRANSITION CHARACTERISTICS
(Slow Roll-Off)
0.1 0.2 0.3 0.4 0.5 0.6
Frequency (x fS)
0.5
0.3
0.1
–0.1
–0.3
–0.5
0
DE-EMPHASIS ERROR (fS = 32kHz)
2 4 6 8 10 12 14
Frequency (kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
0
DE-EMPHASIS ERROR (fS = 44.1kHz)
2 4 6 8 10 12 14 16 18 20
Frequency (kHz)
DE-EMPHASIS ERR0R (fS = 48kHz)
0.5
0.3
0.1
–0.1
–0.3
–0.5
0 2 4 6 8 10 12 14 16 18 20 22
Frequency (kHz)
6

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PCM1600Y pdf, datenblatt
LRCK
BCK
DATA1-DATA3
tBCH
tBCL
tBCY
tDS
tBL
tDH
tLB
SYMBOL
PARAMETER
MIN MAX
tBCY BCK Pulse Cycle Time
48 or 64fS(1)
tBCH
BCK High Level Time
50
tBCL
BCK Low Level Time
50
tBL
BCK Rising Edge to LRCK Edge
30
tLB
LRCK Falling Edge to BCK Rising Edge
30
tDS
DIN Set Up Time
30
tDH
DIN Hold Time
20
NOTE: (1) fS is the sampling frequency (e.g., 44.1kHz, 48kHz, 96kHz, etc.)
FIGURE 5. Audio Interface Timing.
UNITS
ns
ns
ns
ns
ns
ns
50% of VDD
50% of VDD
50% of VDD
MSB
LSB
R/W IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D5 D4 D3 D2 D1 D0
Register Index (or Address)
Read/Write Operation
0 = Write Operation
1 = Read Operation (register index is ignored)
FIGURE 6. Control Data Word Format for MDI.
Register Data
ML
MC
MDI X 0 IDX6 IDX5 IDX4 IDX3 IDX2 IDX1 IDX0 D7 D6 D5 D4 D3 D2 D1 D0 X X D15 D14
FIGURE 7. Write Operation Timing.
REGISTER WRITE OPERATION
SINGLE REGISTER READ OPERATION
All Write operations for the serial control port use 16-bit Read operations utilize the 16-bit control word format shown
data words. Figure 6 shows the control data word format. in Figure 6. For Read operations, the Read/Write (R/W) bit
The most significant bit is the Read/Write (R/W) bit. When is set to ‘1’. Read operations ignore the index bits, IDX[6:0],
set to ‘0’, this bit indicates a Write operation. There are of the control data word. Instead, the REG[6:0] bits in
seven bits, labeled IDX[6:0], that set the register index (or Control Register 11 are used to set the index of the register
address) for the Write operation. The least significant eight that is to be read during the Read operation. Bits IDX[6:0]
bits, D[7:0], contain the data to be written to the register
specified by IDX[6:0].
should be set to 00H for Read operations.
Figure 8 details the Read operation. First, Control Register
Figure 7 shows the functional timing diagram for writing the 11 must be written with the index of the register to be read
serial control port. ML is held at a logic ‘1’ state until a back. Additionally, the INC bit must be set to logic ‘0’ in
register needs to be written. To start the register write cycle, order to disable the Auto-Increment Read function. The
ML is set to logic ‘0’. Sixteen clocks are then provided on Read cycle is then initiated by setting ML to logic ‘0’ and
MC, corresponding to the 16-bits of the control data word on setting the R/W bit of the control data word to logic ‘1’,
MDI. After the sixteenth clock cycle has completed, ML is indicating a Read operation. MDO remains at a high-imped-
set to logic ‘1’ to latch the data into the indexed mode ance state until the last 8 bits of the 16-bit read cycle, which
control register.
®
PCM1600, PCM1601
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