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PCK2023DL Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCK2023DL
Beschreibung CK408 66/100/133/200 MHz spread spectrum differential system clock generator
Hersteller NXP Semiconductors
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Gesamt 30 Seiten
PCK2023DL Datasheet, Funktion
INTEGRATED CIRCUITS
PCK2023
CK408 (66/100/133/200 MHz)
spread spectrum differential system
clock generator
Product data
File under Integrated Circuits — ICL03
2001 Sep 07
Philips
Semiconductors






PCK2023DL Datasheet, Funktion
Philips Semiconductors
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
Product data
PCK2023
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL
PARAMETER
CONDITION
LIMITS
MIN MAX
UNIT
VDD3
DC 3.3 V supply
–0.5 +4.6
V
IIK DC input diode current
VI < 0
— –50 mA
VI DC input voltage
Note 2
——V
IOK DC output diode current
VO > VDD or VO < 0
±50 mA
VO DC output voltage
Note 2
–0.5
VDD + 0.5
V
IO DC output source or sink current
VO = 0 to VDD
±50 mA
Tstg Storage temperature range
–65 +150 °C
Ptot
Power dissipation per package
plastic medium-shrink (SSOP)
For temperature range: –40 to +125°C
above +55°C derate linearly with 11.3 mW/K
850 mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “Recommended Operating Conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
DC OPERATING CONDITIONS
SYMBOL
PARAMETER
CONDITIONS
VDD3
DC 3.3 V supply voltage
AVDD
DC 3.3 V analog supply voltage
VIH 3.3 V input high voltage
VIL 3.3 V input high voltage
VOL3
3.3 V input low voltage
IOL = 1.0 mA
VOH3
3.3 V input high voltage
IOH = 1.0 mA
IIL Input leakage current
0 < VIN < VDD
fref reference frequency, oscillator normal value
CIN Input pin capacitance
CXTAL
Xtal pin capacitance
COUT
Output pin capacitance
LPIN
Pin inductance
Tamb
Operating ambient temperature range in free
air
NOTES:
1. Input leakage current does not include inputs with pull up or pull down resistors.
2. This is a recommendation, not an absolute requirement.
3. As seen by the crystal. Device is intended to be used with a 17–20 pF AT crystal.
LIMITS
MIN MAX
3.135
3.465
3.135
3.465
2.0
VSS – 0.3
VDD + 0.3
0.8
0.4
2.4 —
–5 +5
14.31818 14.31818
—5
13.5 22.5
—6
—7
UNIT
V
V
V
V
V
V
µA
MHz
pF
pF
pF
nH
NOTES
1
2
3
2
2
0 +70 °C
2001 Sep 07
6

6 Page









PCK2023DL pdf, datenblatt
Philips Semiconductors
CK408 (66/100/133/200 MHz) spread
spectrum differential system clock generator
Product data
PCK2023
ALL OUTPUTS
SYMBOL
tPZL/tPZH
tPZL/tPZH
tSTABLE
PARAMETER
output enable delay (all outputs)
output disable delay (all outputs)
all clock stabilization from power-up
LIMITS
Tamb = 0 to +70 °C
MIN MAX
1.0 10.0
1.0 10.0
—3
UNITS
ns
ns
ms
NOTES
11
NOTES:
1. Measured at crossing points or where subtraction of CLK-CLK crosses 0 V.
2. Measured from VOL = 0.175 V to VOH = 0.525 V.
3. These crossing points refer to only crossing points containing a rising edge of a CPU output (as opposed to a CPU output).
4. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
5. Measured from VOL = 0.2 V to VOH = 0.8 V.
6. Determined as a fraction of 2* (tRISE–tFALL)/(tRISE+tFALL).
7. Test load is RS = 33.2 , RP = 49.9 .
8. Period, jitter, offset and skew measured at rising edge @ 1.5 V for 3.3 V clocks.
9. THIGH is measured at 2.4 V for non-CPU outputs.
10. TLOW is measured at 0.4 V for all outputs.
11. The time specified is measured from when VDDQ achieves its normal operating level (typical condition VDDQ = 3.3 V) until the frequency
output is stable and operating within specification.
12. The 3.3 V clock tRISE and tFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC
specification.
13. The average period over any 1 µs period of time must be greater than the minimum specified period.
14. Designed for 150–420 ps (1 V/ns minimum rise time across 0.42 V).
15. Measurement taken from differential waveform.
16. Measurement taken from differential waveform from –0.35 to +0.35 V.
17. Measurements taken from common mode waveforms, measure rise/fall time from 0.41 to 0.86 V. Rise/fall time matching is defined as “the
instantaneous difference between maximum CLK rise (fall) and minimum CLK fall (rise) time, or minimum CLK rise (fall) and maximum CLK
fall (rise) time”. This parameter is designed for waveform symmetry.
18. Measured in absolute voltage, single ended.
19. Cycle-to-cycle jitter measurements taken with minimum capacitive loading on non-CPU outputs.
2001 Sep 07
12

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