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PCK2021DL Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCK2021DL
Beschreibung CK00 100/133 MHz spread spectrum differential system clock generator
Hersteller NXP Semiconductors
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Gesamt 15 Seiten
PCK2021DL Datasheet, Funktion
INTEGRATED CIRCUITS
PCK2021
CK00 (100/133 MHz) spread spectrum
differential system clock generator
Product data
File under Integrated Circuits, ICL03
2001 Oct 11
Philips
Semiconductors






PCK2021DL Datasheet, Funktion
Philips Semiconductors
CK00 (100/133 MHz) spread spectrum differential
system clock generator
Product data
PCK2021
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
CONDITIONS
LIMITS
MIN MAX
UNIT
VDD3
DC 3.3 V supply
–0.5 4.6 V
IIK DC input diode current
VI < 0
— –50 mA
VI DC input voltage
Note 2
–0.5 VDD V
IOK DC output diode current
VO > VDD or VO < 0
±50 mA
VO DC output voltage
Note 2
–0.5
VDD+0.5
V
IO DC output source or sink current
VO = 0 to VDD
±50 mA
Tstg Storage temperature range
–65
+150
°C
Ptot Power dissipation per package
plastic medium-shrink (TSSOP)
For temperature range 0 °C to +70 °C;
above +55 °C derate linearly with 11.3 mW/K
850 mW
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other condition beyond those indicated under “recommended operating condition” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The input and output voltage rating may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
VDD3
AVDD
CL
fref
Tamb
DC 3.3 V supply voltage
DC 3.3 V analog supply voltage
Capacitive load on:
3V666
PCI
48 MHz clock
REF
Reference frequency, oscillator normal value
Operating ambient temperature range in free air
CONDITIONS
1 device load, possible 2
Must meet JEDEC
PCI 2.1 Spec. Requirements
1 device load
1 device load
LIMITS
MIN MAX
3.135
3.465
3.135
3.465
UNIT
V
V
10 30 pF
10 30 pF
10
10
14.31818
0
20
20
14.31818
+70
pF
pF
MHz
°C
POWER MANAGEMENT
CONDITION
Power-down mode (PWRDWN = 0)
Full active 100/133 MHz
MAXIMUM 3.3 V SUPPLY CONSUMPTION
MAXIMUM DISCRETE CAPACITANCE LOADS
VDDL = 3.465 V
ALL STATIC INPUTS = VDD3 OR VSS
60 mA
250 mA
2001 Oct 11
6

6 Page









PCK2021DL pdf, datenblatt
Philips Semiconductors
CK00 (100/133 MHz) spread spectrum differential
system clock generator
PWRDWN
HOST CLK
(INTERNAL)
PCICLK
(INTERNAL)
PWRDWN
HOST CLK
(EXTERNAL)
PCICLK
(EXTERNAL)
OSC & VCO
USB (48 MHz)
ÁÁÁÁ
Figure 5. Power management
CRYSTAL
14.318 MHz
VDD
HOST
DUT
HOST_BAR
CL
RS
RS = 33.2
RS
CL
RP = 50
RP = 50
Figure 6. HOST CLOCK measurements
SW00671
3.3V CLOCKING
INTERFACE
2.4 V
1.5 V
0.4 V
tPERIOD
DUTY CYCLE
tHIGH
tRISE
tFALL
tLOW
Figure 7. 3.3 V clock waveforms
SW00943
Product data
PCK2021
SW00669
2001 Oct 11
12

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