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X1286 Schematic ( PDF Datasheet ) - Intersil Corporation

Teilenummer X1286
Beschreibung Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
Hersteller Intersil Corporation
Logo Intersil Corporation Logo 




Gesamt 26 Seiten
X1286 Datasheet, Funktion
New Features
Repetitive Alarms &
Temperature Compensation
2-Wire™ RTC, 256K (32K x 8)
®
Intersil Real Time Clock/Calendar/CPU Supervisor with EEPROM X1286
FEATURES
• Real Time Clock/Calendar
— Tracks time in Hours, Minutes, Seconds and Hun-
dredths of a Second
— Day of the Week, Day, Month, and Year
• 2 Polled Alarms (Non-volatile)
— Settable on the Second, Minute, Hour, Day of the
Week, Day, or Month
— Repeat Mode (periodic interrupts)
• Oscillator Compensation on chip
— Internal feedback resistor and compensation
capacitors
— 64 position Digitally Controlled Trim Capacitor
— 6 digital frequency adjustment settings to
±30ppm
• Battery Switch or Super Cap Input
• 32K x 8 Bits of EEPROM
— 128-Byte Page Write Mode
— 8 modes of Block Lock™ Protection
— Single Byte Write Capability
• High Reliability
— Data Retention: 100 years
— Endurance: 100,000 cycles per byte
• 2-Wire™ Interface interoperable with I2C*
— 400kHz data transfer rate
• Frequency Output (SW Selectable: Off, 1Hz, 100Hz,
or 32.768kHz)
• Low Power CMOS
— 1.25µA Operating Current (Typical)
• Small Package Options
— 8-Lead EIAJ SOIC and 14-Lead TSSOP
APPLICATIONS
• Utility Meters
• HVAC Equipment
• Audio / Video Components
• Set Top Box / Television
• Modems
• Network Routers, Hubs, Switches, Bridges
• Cellular Infrastructure Equipment
• Fixed Broadband Wireless Equipment
• Pagers / PDA
• POS Equipment
• Test Meters / Fixtures
• Office Automation (Copiers, Fax)
• Home Appliances
• Computer Products
• Other Industrial / Medical / Automotive
BLOCK DIAGRAM
32.768kHz
X1
X2
PHZ/IRQ
Select
SCL
SDA
Serial
Interface
Decoder
Control
Decode
Logic
8
OSC
Compensation
Oscillator
Frequency 1Hz
Divider
Timer
Calendar
Logic
Control/
Registers
(EEPROM)
Status
Registers
(SRAM)
Alarm
Time
Keeping
Registers
(SRAM)
Compare
Alarm Regs
(EEPROM)
256K
EEPROM
ARRAY
*I2C is a Trademark of Philips.
REV 1.1 7/8/04
www.intersil.com
Battery
Switch
Circuitry
VCC
VBACK
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X1286 Datasheet, Funktion
X1286
AC Specifications (TA = -40°C to +85°C, VCC = +2.7V to +5.5V, unless otherwise specified.)
Symbol
fSCL
tIN
tAA
tBUF
tLOW
tHIGH
tSU:STA
tHD:STA
tSU:DAT
tHD:DAT
tSU:STO
tDH
tR
tF
Cb
Parameter
SCL Clock Frequency
Pulse width Suppression Time at inputs
SCL LOW to SDA Data Out Valid
Time the bus must be free before a new transmission can start
Clock LOW Time
Clock HIGH Time
Start Condition Setup Time
Start Condition Hold Time
Data In Setup Time
Data In Hold Time
Stop Condition Setup Time
Data Output Hold Time
SDA and SCL Rise Time
SDA and SCL Fall Time
Capacitive load for each bus line
Min.
50(1)
1.3
1.3
0.6
0.6
0.6
100
0
0.6
50
20 +.1Cb(1)(2)
20 +.1Cb(1)(2)
Notes: (1) This parameter is not 100% tested.
(2) Cb = total capacitance of one bus line in pF.
Max. Units
400 kHz
ns
0.9 µs
µs
µs
µs
µs
µs
ns
µs
µs
ns
300 ns
300 ns
400 pF
TIMING DIAGRAMS
Bus Timing
SCL
tSU:STA
SDA IN
SDA OUT
tF tHIGH
tSU:DAT
tHD:STA
tLOW
tHD:DAT
tR
tAA tDH
tSU:STO
tBUF
REV 1.1 7/8/04
www.intersil.com
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6 Page









X1286 pdf, datenblatt
X1286
latches, read two power status and two alarm bits. This
register is separate from both the array and the Clock/
Control Registers (CCR).
Table 2. Status Register (SR)
Addr 7 6 5
003Fh BAT AL1 AL0
Default 0 0 0
4
0
0
3
0
0
2
RWEL
0
10
WEL RTCF
01
BAT: Battery Supply—Volatile
This bit set to “1” indicates that the device is operating
from VBACK, not VCC. It is a read-only bit and is set/reset
by hardware (X1286 interally). Once the device begins
operating from VCC, the device sets this bit to “0”.
AL1, AL0: Alarm bits—Volatile
These bits announce if either alarm 0 or alarm 1 match
the real time clock. If there is a match, the respective
bit is set to ‘1’. The falling edge of the last data bit in a
SR Read operation resets the flags. Note: Only the AL
bits that are set when an SR read starts will be reset.
An alarm bit that is set by an alarm occurring during an
SR read operation will remain set after the read opera-
tion is complete.
RWEL: Register Write Enable Latch—Volatile
This bit is a volatile latch that powers up in the LOW
(disabled) state. The RWEL bit must be set to “1” prior
to any writes to the Clock/Control Registers. Writes to
RWEL bit do not cause a nonvolatile write cycle, so the
device is ready for the next operation immediately after
the stop condition. A write to the CCR requires both the
RWEL and WEL bits to be set in a specific sequence.
WEL: Write Enable Latch—Volatile
The WEL bit controls the access to the CCR and mem-
ory array during a write operation. This bit is a volatile
latch that powers up in the LOW (disabled) state. While
the WEL bit is LOW, writes to the CCR or any array
address will be ignored (no acknowledge will be issued
after the Data Byte). The WEL bit is set by writing a “1”
to the WEL bit and zeroes to the other bits of the Sta-
tus Register. Once set, WEL remains set until either
reset to 0 (by writing a “0” to the WEL bit and zeroes to
the other bits of the Status Register) or until the part
powers up again. Writes to WEL bit do not cause a non-
volatile write cycle, so the device is ready for the next
operation immediately after the stop condition.
RTCF: Real Time Clock Fail Bit—Volatile
This bit is set to a ‘1’ after a total power failure. This is a
read only bit that is set by hardware (X1286 internally)
when the device powers up after having lost all power
to the device. The bit is set regardless of whether VCC
or VBACK is applied first. The loss of only one of the
supplies does not result in setting the RTCF bit. The
first valid write to the RTC after a complete power fail-
ure (writing one byte is sufficient) resets the RTCF bit
to ‘0’.
Unused Bits:
This device does not use bits 3 or 4 in the SR, but must
have a zero in these bit positions. The Data Byte out-
put during a SR read will contain zeros in these bit
locations.
CONTROL REGISTERS
The Control Bits and Registers, described under this
section, are nonvolatile.
Block Protect Bits—BP2, BP1, BP0
The Block Protect Bits, BP2, BP1 and BP0, determine
which blocks of the array are write protected. A write to a
protected block of memory is ignored. The block protect
bits will prevent write operations to one of eight segments
of the array. The partitions are described in Table 3 .
Table 3. Block Protect Bits
000
001
010
011
100
101
110
111
Protected
Addresses
X1286
None
6000h - 7FFFh
4000h - 7FFFh
0000h - 7FFFh
0000h - 007Fh
0000h - 00FFh
0000h - 01FFh
0000h - 03FFh
Array Lock
None (default)
Upper 1/4
Upper 1/2
Full Array
First Page
First 2 pgs
First 4 pgs
First 8 Pgs
Watchdog Timer Control Bits—WD1, WD0
The bits WD1 and WD0 control the period of the
Watchdog Timer. See Table 4 for options.
REV 1.1 7/8/04
www.intersil.com
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