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PDF PCK2002MPW Data sheet ( Hoja de datos )
| Número de pieza | PCK2002MPW | |
| Descripción | 0-300 MHz I2C 1:10 clock buffer | |
| Fabricantes | NXP Semiconductors | |
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INTEGRATED CIRCUITS
PCK2002M
0–300 MHz I2C 1:10 clock buffer
Product data
File under Integrated Circuits ICL03
2001 Jul 19
Philips
Semiconductors
1 page  
Philips Semiconductors
0–300 MHz I2C 1:10 clock buffer
Product data
PCK2002M
AC CHARACTERISTICS
SYMBOL
PARAMETER
TEST CONDITIONS
NOTES
LIMITS
Tamb = 0°C to +70°C
MIN TYP7 MAX
UNIT
TSDRISE
SDRAM rise time
2, 4 1.5 2.0 4.0 V/ns
TSDFALL
SDRAM fall time
2, 4 1.5 2.9 4.0 V/ns
TPLH
SDRAM buffer LH propagation delay
4, 5 1.2 2.7 3.5 ns
TPHL
SDRAM buffer HL propagation delay
4, 5 1.2 2.7 3.5 ns
TPZL, TPZH
SDRAM buffer enable time
4, 5 1.0 2.6 5.0 ns
TPLZ, TPHZ
SDRAM buffer disable time
4, 5 1.0 2.7 5.0 ns
DUTY CYCLE
Output Duty Cycle
Measured at 1.5 V 3, 4, 5
45
52
55 %
TSDSKW
SDRAM Bus CLK skew
1, 4 —
150 250 ps
TDDSKW
Device to device skew
— — 500 ps
NOTES:
1. Skew is measured on the rising edge at 1.5 V.
2. TSDRISE and TSDFALL are measured as a transition through the threshold region VOL = 0.4 V and VOH = 2.4 V (1 mA) JEDEC specification.
3. Duty cycle should be tested with a 50/50% input.
4. Over MIN (20 pF) to MAX (30 pF) discrete load, process, voltage, and temperature.
5. Input edge rate for these tests must be faster than 1 V/ns.
6. Calculated at minimum edge rate (1.5 ns) to guarantee 45/55% duty cycle at 1.5 V. Pulsewidth is required to be wider at the faster edge to
ensure duty cycle specification is met.
7. All typical values are at VCC = 3.3 V and Tamb = 25 °C.
8. Typical is measured with MAX (30 pF) discrete load.
9. Typical is measured with MIN (20 pF) discrete load.
2001 Jul 19
5
5 Page 
Philips Semiconductors
0–300 MHz I2C 1:10 clock buffer
Product data
PCK2002M
TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm
SOT361-1
2001 Jul 19
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet PCK2002MPW.PDF ] | |
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