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WT60P1 Schematic ( PDF Datasheet ) - ETC

Teilenummer WT60P1
Beschreibung Digital Monitor Controller
Hersteller ETC
Logo ETC Logo 




Gesamt 24 Seiten
WT60P1 Datasheet, Funktion
WT60P1
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
GENERAL DESCRIPTION
The WT60P1 is a MTP (Multiple-Time-Programmable) version of WT60xx microcontroller which is
specially designed for digital controlled multi-sync monitor. It contains 8-bit CPU, 16K bytes flash
memory, 288 bytes RAM, 14 PWMs, parallel I/O, SYNC processor, timer, one DDC interface (slave
mode I2C interface with DDC1), one master/slave I2C interface, two 4-bit A/D converters and watch-
dog timer.
FEATURES
* 8-bit 6502 compatible CPU, 4MHz operating frequency
* 16384 bytes flash memory, 288 bytes SRAM
* 8MHz crystal oscillator
* 14 channels 8-bit/62.5kHz PWM outputs (8 open drain outputs & 6 CMOS outputs)
* Sync signal processor with H+V separation, frequency calculation, H/V polarity detection/control
* Three free-running sync signal outputs for burn-in test (64kHz/62.5Hz, 48kHz/75Hz, 31kHz/60Hz)
* Self-test pattern generator generates cross hatch picture
* DDC interface supports VESA DDC1/DDC2B standard
* Master/slave I2C interface
* Watch-dog timer (0.524 second)
* Maximum 25 programmable I/O pins
* One 8-bit programmable timer
* Two 4-bit A/D converter
* One external interrupt request
* Built-in low VDD voltage reset
* +5V power supply
PIN CONFIGURATION
40-Pin PDIP
42-Pin SDIP
DA2
DA1
DA0
RESET/VPP
VDD
GND
OSCO
OSCI
PB5/SDA2
PB4/SCL2
PB3/PAT
PB2
PB1/HLFI
PB0/HLFO
PB6/IRQ
PC7
PC6
PC5
PC4
PC3
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 VSYNC
DA2 1
39 HSYNC
DA1 2
38 DA3
DA0 3
37 DA4
RESET/VPP 4
36 DA5
VDD 5
35 DA6
6
34 DA7
GND 7
33 PA7/HSO
OSCO 8
32 PA6/VSO
OSCI 9
31 PA5/DA13 PB5/SDA2 10
30 PA4/DA12 PB4/SCL2 11
29 PA3/DA11 PB3/PAT 12
28 PA2/DA10
PB2 13
27 PA1/DA9
PB1/HLFI 14
26 PA0/DA8 PB0/HLFO 15
25 SCL1/PD0 PB6/IRQ 16
24 SDA1/PD1
PC7 17
23 PC0/AD0
PC6 18
22 PC1/AD1
PC5 19
21 PC2
PC4 20
PC3 21
42 VSYNC
41 HSYNC
40 DA3
39 DA4
38 DA5
37
36 DA6
35 DA7
34 PA7/HSO
33 PA6/VSO
32 PA5/DA13
31 PA4/DA12
30 PA3/DA11
29 PA2/DA10
28 PA1/DA9
27 PA0/DA8
26 SCL1/PD0
25 SDA1/PD1
24 PC0/AD0
23 PC1/AD1
22 PC2
* I2C is a trademark of Philips Corporation.
* DDC is a trademark of Video Electronics Standard Association (VESA).
Weltrend Semiconductor, Inc.
1






WT60P1 Datasheet, Funktion
WT60P1
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
Port_B :
Pin PB0/HLFO - general purpose I/O pin shared with half frequency output.
Pin PB1/HLFI - general purpose I/O pin shared with half frequency output.
Pin PB2
- general purpose I/O pin.
Pin PB3/PAT - general purpose I/O pin shared with self-test pattern output.
Pin PB4/SCL2 - general purpose I/O pin shared with I2C interface clock pin.
Pin PB5/SDA2 - general purpose I/O pin shared with I2C interface data pin.
Pin PB6/IRQB - general purpose I/O pin shared with interrupt request input.
The source/sink current of port_B is 5mA when as an output. When it is input, an internal pull high
resistor is connected.
Address
0012H
0013H
0013H
R/W
W
W
R
Initial
00H
FFH
--
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
0 PB6OE PB5OE PB4OE PB3OE PB2OE PB1OE PB0OE
1 PB6W PB5W PB4W PB3W PB2W PB1W PB0W
-- PB6R PB5R PB4R PB3R PB2R PB1R PB0R
Bit Name
PB6OE - PB0OE
PB6W - PB0W
PB6R- PB0R
Bit value = “1”
Output enable.
Outputs high level (IOH= -5mA).
Pin is high level.
Bit value = “0”
Output disable (internal pull-up).
Outputs low level (IOL= 5mA).
Pin is low level.
* If IEN_D bit in REG#1AH is “1” and PB6OE bit is "0", the PB6 pin becomes interrupt request
input.
* If ENI2C bit in REG#1EH is “1”, the PB5 and PB4 pins becomes I2C interface pins.
* If ENPAT bit in REG#16H is “1”, the PB3 pin becomes self-test pattern output.
* If ENHALF bit in REG#17H is “1”, the PB1 pin becomes half frequency input and PB0 pin becomes
half frequency output pin.
PBnOE
PBnW
PBnR
5mA
5mA
100uA
Structure of Port B
Pin PB0 to PB6
Weltrend Semiconductor, Inc.
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6 Page









WT60P1 pdf, datenblatt
WT60P1
Digital Monitor Controller
Ver. 1.51 Jul-31-1998
DDC Interface
The DDC interface is a slave mode I2C interface with DDC1 function. It is fully compatible with
VEAS DDC1/2B standard. The functional block diagram is shown in the below.
Internal Data Bus
VSYNC
Data Buffer
ENACK
MUX
Shift Register
Address Compare
I/O
R/W
ADDR
MSB
1010000
Address Register
START/STOP Detect
Handshake Control
SDA
START
STOP
DDC2B
SCL
After power on or reset the DDC interface, it is in DDC1 state. The shift register shifts out data to
SDA pin on the rising edge of VSYNC clock. Data format is an 8-bit byte followed by a null bit. Most
significant bit (MSB) is transmitted first. Every time when the ninth bit has been transmitted, the shift
register will load a data byte from data buffer (REG#18H). After loading data to the shift register, the
data buffer becomes empty and generates an INT0 interrupt. So the program must write one data byte
into REG#18 every nine VSYNC clocks.
Since the default values of data buffer(REG#22) and shift register are FFH, the SDA pin outputs
high level if no data had been written into data buffer after power on reset. When program finished
initialization and set the IEN_D bit to "1", the INT0 will occur because the data buffer is empty. The
INT0 service routine should check the DDC2B bit is "0" and then writes the first EDID data byte into
data buffer. When the second INT0 occurs, the INT0 service routine writes the second EDID data byte
into data buffer and so on.
SDA
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Bit7
VSYNC 1 2 3
Load data to
shift register
INT0
9 10
18 19
IEN_D
Weltrend Semiconductor, Inc.
12

12 Page





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