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PDF PCI9060SD Data sheet ( Hoja de datos )
| Número de pieza | PCI9060SD | |
| Descripción | 12O COMPATIBLE PCI BUS MASTER INTERFACE CHIP FOR ADAPTERS AND EMBEDDED SYSTEMS | |
| Fabricantes | ETC | |
| Logotipo |  |
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PCI 9080 Data Sheet
Version 1.02
July 24, 1997
Website: http://www.plxtech.com
Email: [email protected]
Phone: 408-774-9060
FAX: 408-774-2169
1 page  
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PCI 9080
TABLE OF CONTENTS
3.13.5 Inbound Post List FIFO ..................................................................................................................................................... 41
3.13.6 Outbound Post List FIFO .................................................................................................................................................. 41
3.13.7 Outbound Post Queue ...................................................................................................................................................... 41
3.13.8 Inbound Free Queue......................................................................................................................................................... 41
3.13.9 Outbound Free List FIFO .................................................................................................................................................. 41
3.13.10 I20 Enable Sequence .................................................................................................................................................... 42
4. REGISTERS ...................................................................................................................................................................43
4.1 NEW REGISTER DEFINITIONS SUMMARY .........................................................................................................43
4.1.1 Register Differences between PCI 9080 and PCI 9060, PCI 9060ES, and PCI 9060SD.................................................. 44
4.2 REGISTER ADDRESS MAPPING..........................................................................................................................50
4.2.1 PCI Configuration Registers ............................................................................................................................................. 50
4.2.2 Local Configuration Registers........................................................................................................................................... 51
4.2.3 Runtime Registers ............................................................................................................................................................ 52
4.2.4 DMA Registers.................................................................................................................................................................. 53
4.2.5 Messaging Queue Registers............................................................................................................................................. 54
4.3 PCI CONFIGURATION REGISTERS .....................................................................................................................55
4.3.1 (PCIIDR; PCI:00h, LOC:00h) PCI Configuration ID Register ............................................................................................ 55
4.3.2 (PCICR; PCI:04h, LOC:04h) PCI Command Register ...................................................................................................... 55
4.3.3 (PCISR; PCI:06h, LOC:06h) PCI Status Register............................................................................................................. 56
4.3.4 (PCIREV; PCI:08h, LOC:08h) PCI Revision ID Register .................................................................................................. 56
4.3.5 (PCICCR; PCI:09-0Bh, LOC:09-0Bh) PCI Class Code Register....................................................................................... 57
4.3.6 (PCICLSR; PCI:0Ch, LOC:0Ch) PCI Cache Line Size Register ....................................................................................... 57
4.3.7 (PCILTR; PCI:0Dh, LOC:0Dh) PCI Latency Timer Register ............................................................................................. 57
4.3.8 (PCIHTR; PCI:0Eh, LOC:0Eh) PCI Header Type Register ............................................................................................... 57
4.3.9 (PCIBISTR; PCI:0Fh, LOC:0Fh) PCI Built-In Self Test (BIST) Register ........................................................................... 58
4.3.10 (PCIBAR0; PCI:10h, LOC:10h) PCI Base Address Register for Memory Accesses to Local, Runtime,
and DMA Registers........................................................................................................................................................... 58
4.3.11 (PCIBAR1; PCI:14h, LOC:14h) PCI Base Address Register for I/O Accesses to Local, Runtime, and
DMA Registers.................................................................................................................................................................. 59
4.3.12 (PCIBAR2; PCI:18h, LOC:18h) PCI Base Address Register for Memory Accesses to Local Address Space 0 ............... 59
4.3.13 (PCIBAR3; PCI:1Ch, LOC:1Ch) PCI Base Address Register for Memory Accesses to Local Address Space 1 .............. 60
4.3.14 (PCIBAR4; PCI:20h, LOC:20h) PCI Base Address Register ............................................................................................ 60
4.3.15 (PCIBAR5; PCI:24h, LOC:24h) PCI Base Address Register ............................................................................................ 60
4.3.16 (PCICIS; PCI:28h, LOC:28h) PCI Cardbus CIS Pointer Register ..................................................................................... 61
4.3.17 (PCISVID; PCI:2Ch, LOC:2Ch) PCI Subsystem Vendor ID Register................................................................................ 61
4.3.18 (PCISID; PCI:2Eh, LOC:2Eh) PCI Subsystem ID Register ............................................................................................... 61
4.3.19 (PCIERBAR; PCI:30h, LOC:30h) PCI Expansion ROM Base Register ............................................................................ 61
4.3.20 (PCIILR; PCI:3Ch, LOC:3Ch) PCI Interrupt Line Register ................................................................................................ 61
4.3.21 (PCIIPR; PCI:3Dh, LOC:3Dh) PCI Interrupt Pin Register ................................................................................................. 62
4.3.22 (PCIMGR; PCI:3Eh, LOC:3Eh) PCI Min_Gnt Register ..................................................................................................... 62
©PLX Technology, Inc., 1997
Page vi
Version 1.01
5 Page 
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SECTION 1
PCI 9080
GENERAL DESCRIPTION
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Figure 1-2. PCI 9080 Internal Block Diagram
1.1 APPLICATIONS FOR THE PCI 9080
1.1.1 PCI Adapter Cards
Major PCI adapter card applications for the PCI 9080
include high performance communications, networking,
disk control, multimedia, and video adapters. PCI 9080
moves data between the host PCI bus and adapter local
bus in several ways. First, the local CPU or host
processor may program the DMA controller of the PCI
9080 to move data between the adapter memory and
host PCI bus. Second, PCI 9080 can perform “Direct
Master Transfers,” whereby a local CPU or controller
accesses the PCI bus directly through a PCI master
transfer. PCI 9080 also supports slave transfers in which
another PCI device is the master. Finally, PCI 9080
contains a complete messaging unit with mailbox
registers, doorbell registers, and queue management
pointers that can be used for message passing under
the I2O protocol or a custom protocol.
1.1.2 Embedded Systems
Another application for PCI 9080 is in embedded
systems, such as network hubs and routers, printer
engines, and industrial equipment. In this configuration,
all four of the above-mentioned data transfer modes are
used. In addition, PCI 9080 supports Type 0 and Type 1
PCI configuration cycles, which allows embedded CPU
to act as the embedded system host and to configure
other PCI devices in the system.
©PLX Technology, Inc., 1997
Page 2
Version 1.02
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