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Teilenummer | WS57C45-35S |
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Beschreibung | HIGH-SPEED 2K x 8 REGISTERED CMOS PROM/RPROM | |
Hersteller | STMicroelectronics | |
Logo | ||
Gesamt 9 Seiten WS57C45
HIGH-SPEED 2K x 8 REGISTERED CMOS PROM/RPROM
KEY FEATURES
• Ultra-Fast Access Time
— 25 ns Setup
— 12 ns Clock to Output
• Low Power Consumption
• Fast Programming
• Programmable Synchronous or
Asynchronous Output Enable
• DESC SMD Nos. 5962-88735/5962-87529
• Pin Compatible with AM27S45 and
CY7C245
• Immune to Latch-UP
— Up to 200 mA
• ESD Protection Exceeds 2000 V
• Programmable Asynchronous Initialize
Register
GENERAL DESCRIPTION
The WS57C45 is an extremely High Performance 16K UV Erasable Registered CMOS RPROM. It is a direct
drop-in replacement for such devices as the AM27S45 and CY7C245.
To meet the requirements of systems which execute and fetch instructions simultaneously, an 8-bit parallel data
register has been provided at the output which allows RPROM data to be stored while other data is being
addressed.
An asynchronous initialization feature has been provided which enables a user programmable 2049th word to be
placed on the outputs independent of the system clock. This feature can be used to force an initialize word or
provide a preset or clear function.
A further advantage of the WS57C45 over Bipolar PROM devices is the fact that it utilizes a proven EPROM
technology. This enables the entire memory array to be tested for switching characteristics and functionality after
assembly. Unlike devices which cannot be erased, every WS57C45 RPROM in a windowed package is 100%
tested with worst case test patterns both before and after assembly.
PIN CONFIGURATION
TOP VIEW
Chip Carrier
NC
A5 A6 A7 VCC A8 A9
A4
4
5
3
2
1
28 27 26
25
A10
A3 6
24 INIT/VPP
A2 7
23 OE/OES
A1 8
22 CP/PGM
A0 9
21 NC
NC 10
20 O7
O0 11
19 O6
12 13 14 15 16 17 18
O1 O2 NC O3 O4 O5
GND
CERDIP/Plastic DIP/
Flatpack
A7
A6
A5
A4
A3
A2
A1
A0
O0
O1
O2
GND
1
2
3
4
5
6
7
8
9
10
11
12
24 VCC
23 A8
22 A9
21 A10
20 INIT/VPP
19 OE/OES
18 CP/PGM
17 O7
16 O6
15 O5
14 O4
13 O3
PRODUCT SELECTION GUIDE
PARAMETER
Set Up Time (Max)
Clock to Output (Max)
WS57C45-25
25 ns
12 ns
Return to Main Menu
WS57C45-35
35 ns
15 ns
WS57C45-45
45 ns
25 ns
2-21
WS57C45
Synchronous Enable Programming
The WS57C45 contains both a synchronous and asynchronous enable feature. The part is delivered configured in
the asynchronous mode and only requires alteration if the synchronous mode is required. This is accomplished by
programming an on-chip EPROM cell. Similar to the Initial Byte, this function is enabled and addressed by using a
super voltage. Referring to the Mode Selection table, VPP is applied to A1 followed by VIH applied to A2. This
procedure addresses the EPROM cell that programs the synchronous enable feature. The EPROM cell is
programmed with a 10 ms program pulse on CP/PGM. It does not require any data since there is no selection as to
how synchronous enable may be programmed, only if it is to be programmed.
Synchronous Enable Verification
The WS57C45’s synchronous enable function is verified operationally. Apply power for read operation with OE/OES
and INIT/VPP at VIH and take the clock (CP/PGM) from VIL to VIH. The output data bus should be in a high
impedance state. Next take OE/OES to VIL. The outputs will remain in the high impedance state. Take the clock
(CP/PGM) from VIL to VIH and the outputs will now contain the data that is present. Take OE/OES to VIH. The output
should remain driven. Clocking CP/PGM once more from VIL to VIH should place the outputs again in a high
impedance state.
Blank Check
Upon delivery from WaferScale Integration, Inc. or after each erasure (see Erasure section), the WS57C45 has all
2048 bytes in the ‘0’ state. “1’s” are loaded into the WS57C45 through the procedure of programming.
MODE
READ OR OUTPUT DISABLE
PIN FUNCTION
A2 CP/PGM (OE/OES)/VFY INIT/VPP
Read (Note 6)
Output Disable
Program (Notes 5 & 7)
Program Verify (Notes 5 & 7)
Program Inhibit (Notes 5 & 7)
Intelligent Program (Notes 5 & 7)
Program Synch Enable (Note 7)
Program Initial Byte (Note 7)
Initial Byte Read
XX
XX
X VIL
X VIH
X VIH
X VIL
VIH VIL
VIL VIL
XX
VI L
VI H
VI H
VI L
VI H
VI H
VI H
VI H
VI L
NOTES: 5. X = Don’t Care but not to exceed VPP.
6. During read operation, the output latches are loaded on a “0” to “1” transition of CP.
7. During programming and verification, all unspecified pins to be at VIL.
VI H
VI H
VPP
VPP
VPP
VPP
VPP
VPP
VI L
OUTPUTS
A1
X Data Out
X High Z
X Data In
X Data Out
X High Z
X Data In
VPP High Z
VPP Data In
X Data Out
2-26
6 Page | ||
Seiten | Gesamt 9 Seiten | |
PDF Download | [ WS57C45-35S Schematic.PDF ] |
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