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PDF WM8803 Data sheet ( Hoja de datos )
| Número de pieza | WM8803 | |
| Descripción | DIGITAL AUDIO INTERFACE RECEIVER | |
| Fabricantes | Wolfson Microelectronics plc | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de WM8803 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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WM8803
Digital Audio Interface Receiver
DESCRIPTION
The WM8803 is a digital audio interface receiver conforming
to IEC 60958/61937 and EIAJ CP-1201. It supports input
audio data rates up to 192kHz and a maximum output data
length of 24 bits.
The WM8803 has a flexible digital output port that allows the
user access to channel status pre-emphasis information, input
signal sampling frequency, sub-code Q data with the
associated CRC flags and other status data.
The WM8803 can output an externally input clock signal that
can be used as an ADC converter clock when the PLL is
unlocked. It also maintains the continuity of the output clock
when the clock is switched.
The WM8803 includes a built-in oscillator and serial data
input circuits and allows the system micro-controller to read
the sub-code Q data and the channel status. It provides
several low-power modes, thus supporting applications that
require long battery life, such as portable audio devices and
PDAs.
The device is available in a 24-pin TSSOP package.
FEATURES
• PLL circuit for synchronization with transferred input bi-
phase mark signal.
• Input sampling frequency: 32kHz to 192kHz
• Outputs clocks: fs, 64fs, and one of 128fs, 256fs, 384fs,
and 512fs.
• 4-Wire CCB MPU Serial Control or Hardware Default
Interface
• Master Clocking Mode
• Programmable Audio Data Interface Modes
− I2S, Left, Right Justified
− 16/20/24/32 bit Word Lengths
• 3.3V Digital supply Operation
• 5V tolerant digital input ports
APPLICATIONS
• DVD Receivers
• DVD-R/W Players
• Audio Video Receivers
• Portable Music Players
BLOCK DIAGRAM
DI CL CE
AUDIO PD
DO
E/INT
MICROCONTROLLER INTERFACE
W
WM8803
DVDD
DGND
UGPI
RXIN
DEMODULATION
AND LOCK
DETECTION
FS
CALCULATOR
DATA
BUFFER
C&U
ERROR
LPF
XIN
XOUT
PLL
AMP
CLOCK
SELECTOR
AVDD AGND
WOLFSON MICROELECTRONICS plc
w :: www.wolfsonmicro.com
AUDIO
INTERFACE
SDIN
CLKOUT
BCLK
LRCLK
SDATO
Product Preview, September 2003, Rev 1.1
Copyright 2003 Wolfson Microelectronics plc
1 page  
Product Preview
WM8803
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating
beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Ele
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically suscept
damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
device.
CONDITION
Maximum supply voltage
Maximum supply voltage
Input voltage 1
Input voltage 2
Storage temperature
Operating temperature
Maximum output current
Notes:
1. AVDD pin
2. DVDD pin
3. XIN pin
4. RXIN, SDIN, PD, CE, CL, and DI pins
5. Per single input or output pin
SYMBOL
AVDDmax
DVDDmax
VIN1
VIN2
Tstg
Topg
Ii, Io
CONDITIONS
1
2
3
4
5
MIN - MAX
–0.3 to 4.6V
–0.3 to 4.6V
–0.3 to VDD + 0.3V
–0.3 to 5.8V
–55 to 125°C
–30 to 70°C
±20 mA
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Supply voltage 1
Supply voltage 2
Input voltage range 1
Input voltage range 2
Operating temperature
Notes:
SYMBOL
AVDD, DVDD
AVDD, DVDD
VIN1
VIN2
Topg
TEST CONDITIONS
1
2
3
4
MIN
2.7
3.0
0
0
–30
TYP
3.3
3.3
3.3
3.3
—
MAX
3.6
3.6
3.6
5.5
70
UNIT
V
V
V
V
°C
1. PLLCK [1:0] = “00” or PLLCK [1:0] = “01”
2. PLLCK [1:0] = “10” or PLLCK [1:0] = “11”
3. XIN pin
4. RXIN, SDIN, PD , CE, CL, and DI pins
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PP Rev 1.1 September 2003
5
5 Page 
Product Preview
CLOCKS
WM8803
PLL (LPF)
The WM8803 includes a VCO (voltage controlled oscillator) that can synchronize with data
corresponding to sampling frequencies from 30k to 195kHz.
The locking frequency is selected by setting PLLCK[1:0].
The VCO circuit can be stopped by setting PLLOPR.
The range of input data that can be received depends upon the settings of the PLLCK[1:0].
The (512/2)fs entry for the PLLCK[1:0] = “11” in Table 3 is a state where the PLL itself is
synchronized with the 512fs clock, but the clock signal output from CLKOUT is a frequency 1/2 that
of the PLL locked frequency i.e.256fs. This (512/2)fs lock frequency has the same functions as the
256fs setting from CLKOUT and can be convenient for certain applications. Refer to the output
clocks section for details.
It is recommended that the 256fs setting of PLLCK[1:0] = “00” is used to reduce the system power
consumption, especially in portable equipment.
For best performance, it is recommended that the 512fs setting of PLLCK[1:0] = “10” or the (512/2)fs
of PLLCK[1:0] = “11” is used.
PLLCK1 PLLCK0
PLL LOCK FREQUENCY
INPUT DATA RECEPTION RANGE
00
256fs
30k to 195kHz
01
384fs
30k to 108kHz
10
512fs
30k to 108kHz
11
(512/2)fs
30k to 108kHz
Table 3 Input Data Reception Ranges by PLL Lock Frequency Setting
The LPF is the PLL loop filter connection. Use capacitor and resistor components of the
recommended values as listed in the table below according to the PLLCK[1:0] settings used.
PLLCK1
0
0
1
PLLCK0
0
1
0
11
Table 4 Loop Filter Component Values
R0
150Ω
150Ω
C0
0.047µF
0.068µF
C1
0.0068µF
0.0047µF
LPF
R0 C1
C0
Figure 4 Loop Filter Structure
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PP Rev 1.1 September 2003
11
11 Page | ||
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| PDF Descargar | [ Datasheet WM8803.PDF ] | |
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