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PDF WM8738 Data sheet ( Hoja de datos )
| Número de pieza | WM8738 | |
| Descripción | 24 BIT STEREO ADC | |
| Fabricantes | Wolfson Microelectronics plc | |
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24-Bit Stereo ADC
WM8738
DESCRIPTION
The WM8738 is a high performance stereo audio ADC
designed for consumer applications.
Stereo line-level audio inputs are provided, along with a
control input pin to allow operation of the audio interface in
either one of two industry standard modes. The device also
has a selectable digital high pass filter to remove residual
DC offsets.
Stereo 24-bit multi-bit sigma delta ADCs are provided, along
with oversampling digital interpolation filters. 24-bit digital
audio output word lengths and sampling rates from 32kHz to
96kHz are supported.
The device is available in a small 14-lead SOIC package.
FEATURES
Audio Performance
- 90 dB SNR (‘A’ weighted @ 48kHz)
3.0 – 5.5V Analogue Supply Operation
3.0 – 3.6V Digital Supply Operation
ADC Sampling Frequency: 32kHz – 96kHz
Selectable ADC High Pass Filter
Selectable Audio Data Interface Modes
- I2S or Left Justified
14-lead SOIC Package
APPLICATIONS
CD and Minidisc Recorders
DVD Players
General Purpose Audio Conversion
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
To receive regular email updates, sign up at http://www.wolfsonmicro.com/enews
Production Data, February 2012, Rev 4.5
Copyright 2012 Wolfson Microelectronics plc
1 page  
WM8738
Production Data
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage
conditions prior to surface mount assembly. These levels are:
MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag.
MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag.
CONDITION
MIN MAX
Digital supply voltage
-0.3V
+4.2V
Analogue supply voltage
-0.3V
+7.0V
Voltage range digital inputs
DGND -0.3V
+7.0V
Voltage range analogue inputs
AGND -0.3V
AVDD +0.3V
Master Clock Frequency
37MHz
Operating temperature range, TA
Storage temperature prior to soldering
-40C
+85C
30C max / 85% RH max
Storage temperature after soldering
-65C
+150C
Notes
1. Analogue and digital grounds must always be within 0.3V of each other.
2. The digital supply voltage must always be less than or equal to the analogue supply voltage.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
Digital supply range
Analogue supply range
Ground
Analogue supply current
Analogue supply current
Supply Current Low Power
Mode
Supply Current Low Power
Mode
Digital supply current
SYMBOL
DVDD
AVDD
DGND,AGND
TEST
CONDITIONS
MIN
3.0
3.0
AVDD = 5.0V,
(DVDD at 3.3V)
AVDD = 3.3V,
(DVDD at 3.3V)
AVDD = 5.0V
(DVDD at 3.3V)
AVDD = 3.3V
(DVDD at 3.3V)
DVDD = 3.3V
AVDD = 5.0V or 3.3V
TYP
0
30
19
180
110
4
MAX
3.6
5.5
UNIT
V
V
V
mA
mA
A
A
mA
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PD, Rev 4.5, February 2012
5
5 Page 
WM8738
Production Data
In a real application the designer is unlikely to have control of the relative power up sequence of
AVDD and DVDD. Using the POR circuit to monitor CAP ensures a reasonable delay between
applying power to the device and Device Ready.
Figure 3 and Figure 4 show typical power up scenarios in a real system. Both AVDD and DVDD must
be established and CAP must have reached the threshold Vporr before the device is ready and can be
written to. Any writes to the device before Device Ready will be ignored.
Figure 3 shows DVDD powering up before AVDD. Figure 4 shows AVDD powering up before DVDD.
In both cases, the time from applying power to Device Ready is dominated by the charge time of
CAP.
A 10uF cap is recommended for decoupling on CAP. The charge time for CAP will dominate the time
required for the device to become ready after power is applied. The time required for VMIDADC to
reach the threshold is a function of the CAP resistor string and the decoupling capacitor. The
Resistor string has a typical equivalent resistance of 50k (+/-20%). Assuming a 10uF capacitor, the
time required for CAP to reach threshold of 1V is approx 110ms.
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PD, Rev 4.5, February 2012
11
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet WM8738.PDF ] | |
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