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WM8737GEFL Schematic ( PDF Datasheet ) - Wolfson Microelectronics plc

Teilenummer WM8737GEFL
Beschreibung STEREO ADC WITH MICROPHONE PREAMPLIFIER
Hersteller Wolfson Microelectronics plc
Logo Wolfson Microelectronics plc Logo 




Gesamt 30 Seiten
WM8737GEFL Datasheet, Funktion
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WM8737L
Stereo ADC with Microphone Preamplifier
DESCRIPTION
The WM8737L is a low power stereo audio ADC designed
specifically for portable applications such as minidisc and
memory audio / voice recorders.
The device offers three sets of stereo inputs, which can be
configured for line-level signals, for internal or table-top
microphones, or for DC measurement (battery monitor). A
programmable gain amplifier can be used for automatic
level control (ALC) with user programmable hold, attack and
decay times. The device also has a selectable high pass
filter to remove residual DC offsets.
If the signal source is mono, the WM8737L can run in mono
mode, saving power. It can also mix two channels to mono,
either in the analogue or the digital domain.
Master or slave mode clocking schemes are offered. Stereo
24-bit multi-bit sigma-delta ADCs are used with digital audio
output word lengths from 16-32 bits, and sampling rates
from 8kHz to 96kHz supported.
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including gain
controls, analogue or digital mono mixing, and power
management facilities. The device is supplied in a leadless
5x5mm QFN package.
FEATURES
SNR 97dB (‘A’ weighted @ 3.3V, 48kHz, normal power
mode)
THD –85dB (at –1dB, 3.3V, normal power mode)
Complete Stereo / Mono Microphone Interface
- Programmable microphone preamp
- Automatic Level Control
- Low-noise microphone bias voltage
Configurable Power / Performance
Low Power Mode
- 8.5mW at AVDD = 1.8V (stereo, mic preamps off)
- 20mW at AVDD = 3.3V (stereo, mic preamps off)
Low Supply Voltages
- Analogue 1.8V to 3.6V
- Digital core: 1.42V to 3.6V
- Digital I/O: 1.8V to 3.6V
256fs / 384fs or USB master clock rates: 12MHz, 24MHz
Audio sample rates: 8, 11.025, 12, 16, 22.05, 24, 32, 44.1,
48, 88.2, 96kHz generated internally from master clock
32-pin QFN package, 5 x 5 x 0.9mm
APPLICATIONS
Memory Audio / Voice Recorders
Minidisc Recorders
Portable Digital Music Systems
BLOCK DIAGRAM
WOLFSON MICROELECTRONICS plc
www.wolfsonmicro.com
Advanced Information, May 2004, Rev 3.0
Copyright 2004 Wolfson Microelectronics plc






WM8737GEFL Datasheet, Funktion
WM8737L
Preliminary Technical Data
ELECTRICAL CHARACTERISTICS
Test Conditions
DCVDD = 1.5V, AVDD = MVDD = 3.3V, TA = +25oC, 1kHz -0.5dBFS signal, Normal Power Mode, fs = 48kHz, PGA gain = 0dB,
24-bit audio data, unless otherwise stated. Microphone preamplifier at maximum bias (default) and gain 13dB, unless otherwise
stated.
PARAMETER
SYMBOL TEST CONDITIONS
MIN
TYP
MAX
UNIT
Microphone Preamplifier (LINPUT1/2/3, RINPUT1/2/3) to ADC
Microphone Pre-amp (Boost)
MICBOOST = 00
13
dB
Gain
MICBOOST = 01
18
MICBOOST = 10
28
MICBOOST = 11
33
Microphone preamplifier noise
(referred to input)
(A-weighted)
Voltage at 1kHz
Micboost gain = 28dB
at 20Hz – 20kHz
6
0.7
nV / Hz
µV rms
Micboost gain = 28dB
-123
dBV
Input Offset Voltage
1 5 mV
Microphone preamplifier Signal
SNR
AVDD = 3.3V
109
dB
to Noise Ratio
600Rsource
(A-weighted)
AVDD=1.8V
102
(Note 1)
600Rsource
28 dB gain,
94
AVDD = 3.3V
Dynamic Range (Note 2)
DNR
600Rsource
A-weighted, -60dBFS
Gain = 0dB
94
dB
Total Harmonic Distortion
THD
13dB gain,
-74 dB
(Note 3)
AVDD = 3.3V, Single
Channel
0.0056
%
13dB gain,
-73
AVDD=1.8V, Single
Channel
0.02
Channel Separation
-65 dB
Power Supply Rejection Ratio
PSRR
1kHz, 100mV pk-pk,
60
dB
Input Leakage
Microphone
-10
1
10 µA
preamplifier enabled
Input Resistance
500k
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AI Rev 3.0 May 2004
6

6 Page









WM8737GEFL pdf, datenblatt
WM8737L
Preliminary Technical Data
Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
50
ns
BCLK pulse width high
BCLK pulse width low
tBCH
tBCL
20
20
ns
ns
ADCLRC set-up time to BCLK rising edge
tLRSU
10
ns
ADCLRC hold time from BCLK rising edge
tLRH
10
ns
ADCDAT propagation delay from BCLK falling edge
tDD 0
10 ns
CONTROL INTERFACE TIMING – 3-WIRE MODE
CSB
tCSL
SCLK
tSCY
tSCH
tSCL
tCSH
tSCS
tCSS
SDIN
tDSU
tDHO
LSB
Figure 4 Control Interface Timing – 3-Wire Serial Control Mode
Test Conditions
DBVDD = 3.3V, DCVDD = 1.42 to 3.6V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless
otherwise stated.
PARAMETER
SYMBOL
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising edge
SCLK pulse cycle time
tSCS
tSCY
40
80
ns
ns
SCLK pulse width low
tSCL 40
ns
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
tSCH
tDSU
tDHO
40
10
10
ns
ns
ns
CSB pulse width low
tCSL 10
ns
CSB pulse width high
CSB rising to SCLK rising
Pulse width of spikes which will be suppressed
tCSH
tCSS
tSP
10
10
0
ns
ns
5 ns
CONTROL INTERFACE TIMING – 2-WIRE MODE
SDIN
SCLK
t3
t6
t1
t5
t2
t7
t9
t3
t4
t8
Figure 5 Control Interface Timing – 2-Wire Serial Control Mode
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AI Rev 3.0 May 2004
12

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