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WM8192 Schematic ( PDF Datasheet ) - Wolfson Microelectronics plc

Teilenummer WM8192
Beschreibung (8+8) Bit Output 16-bit CIS/CCD AFE/Digitiser
Hersteller Wolfson Microelectronics plc
Logo Wolfson Microelectronics plc Logo 




Gesamt 24 Seiten
WM8192 Datasheet, Funktion
WM8192
(8 + 8) Bit Output 16-bit CIS/CCD AFE/Digitiser
Product Preview, June 2000, Rev 1.0
DESCRIPTION
The WM8192 is a 16-bit analogue front end/digitiser IC
which processes and digitises the analogue output signals
from CCD sensors or Contact Image Sensors (CIS) at pixel
sample rates of up to 6MSPS.
The device includes three analogue signal processing
channels each of which contains Reset Level Clamping,
Correlated Double Sampling and Programmable Gain and
Offset adjust functions. Three multiplexers allow single
channel processing. The output from each of these
channels is time multiplexed into a single high-speed 16-bit
Analogue to Digital Converter. The digital output data is
available in 8 or 4-bit wide multiplexed format.
An internal 4-bit DAC is supplied for internal reference level
generation. This may be used during CDS to reference CIS
signals or during Reset Level Clamping to clamp CCD
signals. An external reference level may also be supplied.
ADC references are generated internally, ensuring optimum
performance from the device.
Using an analogue supply voltage of 5V and a digital
interface supply of either 5V or 3.3V, the WM8192 typically
only consumes 240mW when operating from a single
5V supply.
FEATURES
16-bit ADC
6MSPS conversion rate
Low power – 240mW typical
5V single supply or 5V/3.3V dual supply operation
Single or 3 channel operation
Correlated double sampling
Programmable gain (8-bit resolution)
Programmable offset adjust (8-bit resolution)
Programmable clamp voltage
8 or 4-bit wide multiplexed data output formats
Internally generated voltage references
28-pin SOIC package
Serial control interface
APPLICATIONS
Flatbed and sheetfeed scanners
USB compatible scanners
Multi-function peripherals
High-performance CCD sensor interface
BLOCK DIAGRAM
VRLC/VBIAS
(26)
VSMP MCLK
(5) (7)
AVDD DVDD1 DVDD2
(21) (3) (10)
VRT VRX VRB
(24) (25) (23)
RINP (1)
GINP (28)
BINP (27)
CL
RLC
RLC
RS VS
M
U
X
TIMING CONTROL
CDS
RM
GU
X
B
8
OFFSET
DAC
VREF/BIAS
+ PGA
RM
GU
X
B
I/P SIGNAL
8 POLARITY
ADJUST
CDS
+ PGA
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
+
M
+U
X
WM8192
16-
BIT
ADC
DATA
I/O
PORT
(4) OEB
(13) OP[0]
(14) OP[1]
(15) OP[2]
(16) OP[3]
(17) OP[4]
(18) OP[5]
(19) OP[6]
(20) OP[7]/SDO
RLC
RLC 4
DAC
CDS
+ PGA
+
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
CONFIGURABLE
SERIAL
CONTROL
INTERFACE
(9) SEN
(12) SCK
(11) SDI
(6) RLC/ACYC
(22)
AGND1
(2)
AGND2
(8)
DGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
http://www.wolfson.co.uk
Product Preview data sheets contain
specifications for products in the formative
phase of development. These products may
be changed or discontinued without notice.
2000 Wolfson Microelectronics Ltd.






WM8192 Datasheet, Funktion
WM8192
INPUT VIDEO SAMPLING
tPER
tMCLKH tMCLKL
MCLK
VSMP
INPUT
tVSMPSU
tVSMPH
tVSU
tVH
VIDEO
Product Preview
tRSU
tRH
Figure 1 Input Video Timing
Note:
1. See Page 14 (Programmable VSMP Detect Circuit) for video sampling description.
Test Conditions
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated
PARAMETER
MCLK period
SYMBOL
tPER
TEST CONDITIONS
MIN
83.3
MCLK high period
tMCLKH
37.5
MCLK low period
tMCLKL
37.5
VSMP set-up time
tVSMPSU
10
VSMP hold time
tVSMPH
5
Video level set-up time
tVSU
15
Video level hold time
tVH
5
Reset level set-up time
tRSU
15
Reset level hold time
tRH
5
Notes:
1. tVSU and tRSU denote the set-up time required after the input video signal has settled.
2. Parameters are measured at 50% of the rising/falling edge.
TYP
MAX
UNITS
ns
ns
ns
ns
ns
ns
ns
ns
ns
OUTPUT DATA TIMING
MCLK
OP[7:0]
Figure 2 Output Data Timing
tPD
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 June 2000
6

6 Page









WM8192 pdf, datenblatt
WM8192
Product Preview
OUTPUT FORMATS
The digital data output from the ADC is available to the user in 8 or 4-bit wide multiplexed formats by
setting control bit MUXOP. Latency of valid output data with respect to VSMP is programmable by
writing to control bits DEL[1:0]. The latency for each mode is shown in the Operating Mode Timing
Diagrams section.
Figure 9 shows the output data formats for Modes 1 2 and 4 6. Figure 10 shows the output data
formats for Mode 3. Table 1 summarises the output data obtained for each format.
MCLK
8+8-BIT
OUTPUT
4+4+4+4-BIT
OUTPUT
AB
AB CD
MCLK
8+8-BIT
OUTPUT
AB
4+4+4+4-BIT
OUTPUT
ABABC D
Figure 9 Output Data Formats
(Modes 1 2, 4 6)
Figure 10 Output Data Formats
(Mode 3)
OUTPUT
FORMAT
MUXOP
OUTPUT
PINS
OUTPUT
8+8-bit
0 OP[7:0] A = d15, d14, d13, d12, d11, d10, d9, d8
multiplexed
B = d7, d6, d5, d4, d3, d2, d1,d0
4+4+4+4-bit 1 OP[7:4] A = d15, d14, d13, d12
(nibble)
B = d11, d10, d9, d8
C = d7, d6, d5, d4
D = d3, d2, d1, d0
Table 1 Details of Output Data Shown in Figure 9 and Figure 10.
WOLFSON MICROELECTRONICS LTD
PP Rev 1.0 June 2000
12

12 Page





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