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WM8143-12 Schematic ( PDF Datasheet ) - Wolfson Microelectronics plc

Teilenummer WM8143-12
Beschreibung 12-bit/4MSPS CCD Signal Processor
Hersteller Wolfson Microelectronics plc
Logo Wolfson Microelectronics plc Logo 




Gesamt 24 Seiten
WM8143-12 Datasheet, Funktion
WM8143-12
12-bit/4MSPS CCD Signal Processor
Production Data Nov. 1999 Rev 4
Description
The WM8143-12 integrates the analogue signal
conditioning required by CCD sensors with a 12-bit ADC.
The WM8143-12 requires minimal external circuitry and
provides a cost-effective sensor to digital domain system
solution.
Each of the three analogue conditioning channels
includes reset level clamp, CDS, fine offset level shifting
and programmable gain amplification. The three channels
are multiplexed into the ADC. The output from the ADC is
fed to the output bus pins OP[11:0] via a 12/8 bit
multiplexer, enabled by the OEB signal.
The flexible output architecture allows twelve-bit data to
be accessed either on a twelve-bit bus or via a time-
multiplexed eight-bit bus. The WM8143-12 can be
configured for pixel-by-pixel or line-by-line multiplexing
operation. Reset level clamp and/or CDS features can be
optionally bypassed. The device configuration is
programmed either via a simple serial interface or via an
eight-bit parallel interface.
The serial/parallel interfaces of the WM8143-12 are
control compatible with those of the WM8144-10 and
WM8144-12.
Features
Reset level clamp
Correlated double sampling (CDS)
Fine offset level shifting
Programmable gain amplification
12-bit ADC with maximum 4 MSPS
Simple clocking scheme
Control by serial or parallel interface
Time multiplexed eight-bit data output mode
32 pin TQFP package
Interface compatible with WM8144-10 and
WM8144-12
Applications
Flatbed scanners
Sheet feed scanners
Film scanners
CCD sensor interfaces
Contact image sensor (CIS) interfaces
Block Diagram
VRLC
VRU VRT
VRB
VMID
VSMP MCLK RLC
AGND DGND DVDD AVDD
VMID
RINP
GINP
BINP
CL RS VS
S/H
S/H
CDS
S/H
S/H
CDS
MUX
PGA
5-BIT REG
PGA
5-BIT REG
S/H
S/H
CDS
PGA
5-BIT REG
TIMING CONTROL
OFFSET
++
8-BIT +
SIGN DAC
VMID
OFFSET
++
8-BIT +
SIGN DAC
VMID
OFFSET
++
8-BIT +
SIGN DAC
VMID
M
U
X
WM8143-12
12-bit
ADC
12/8
MUX
CONFIGURABLE
SERIAL/PARALLEL
CONTROL INTERFACE
OEB
OP[11:0]
SDI / DNA
SCK / RNW
SEN / STB
NRESET
Production Data datasheets contain
final specifications current on
publication date. Supply of products
conforms to Wolfson
Microelectronics' terms and
conditions.
Wolfson Microelectronics ©1999 Wolfson Microelectronics Ltd.
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386 Fax +44 (0) 131 667 5176
www: http://www.wolfson.co.uk






WM8143-12 Datasheet, Funktion
WM8143-12
Production Data
Pin Description
PIN NAME
1 OP[2]
2 OP[3]
3 OP[4]
4 OP[5]
5 OP[6]
6 OP[7]
7 OP[8]
8 OP[9]
9 OP[10]
10 OP[11]
11 NRESET
12 AVDD
13 AGND
14 VRU
15 VRB
16 VRT
17 VMID
18 VRLC
19 BINP
20 GINP
21 RINP
22 OEB
23 SEN/STB
24 SDI/DNA
25 SCK/RNW
26 RLC
27 VSMP
TYPE
Digital OP
Digital OP
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IO
Digital IP
Analogue supply
Analogue supply
Analogue IP
Analogue OP
Analogue OP
Analogue OP
Analogue OP
Analogue IP
Analogue IP
Analogue IP
Digital IP
Digital IP
Digital IP
Digital IP
Digital IP
Digital IP
DESCRIPTION
Tri-state digital 12-bit bi-directional bus. There are four modes:
Tri-state:
when OEB = 1
Output twelve-bit:
twelve bit data is output from bus
Output 8-bit multiplexed:
data output on OP[11:4] at 2 * ADC
conversion Rate
Input 8-bit:
control data is input on bits OP[11:4] in
parallel mode when SCK/RNW = 0.
MSB of the output word is OP[11], LSB is OP[0]
Reset input, active low. This signal forces a reset of all internal registers and selects
whether the serial control bus or parallel control bus is used (see SEN/STB)
Positive analogue supply (5V)
Analogue ground (0V)
ADC reference voltages. The ADC reference range is applied between VRT (full
scale) and VRB (zero level). VRU can be used to derive optimal reference voltages
from an external 5V reference
Buffered mid-point of ADC reference string
Selectable analogue output voltage for RLC
Blue channel input video
Green channel input video
Red channel input video
Output tri-state control:
all outputs enabled when OEB = 0
Serial interface:
enable, active high
Parallel interface:
strobe, active low
Latched on NRESET rising edge: If low then device control is by serial interface, if
high then device control is by parallel interface
Serial interface:
serial interface input data signal
Parallel interface:
high = data, low = address
Serial interface:
serial interface clock signal
Parallel interface:
high = OP[11:4] is output bus
low = OP[11:4] is input bus
Selects whether reset level clamp is applied on a pixel-by-pixel basis. If RLC is
required on each pixel then this pin can be tied high
Video sample synchronisation pulse. This signal is applied synchronously with
MLCK to specify the point in time that the input is sampled. The timing of internal
multiplexing between the R, G and B channels is derived from this signal.
Wolfson Microelectronics
6
PD. Rev 4 Nov 99

6 Page









WM8143-12 pdf, datenblatt
WM8143-12
When the VS/RS control is activated the switch closes
and the effective impedance of the input is 1/CF where
the value of C changes from 0.3pF for minimum gain to
9.6pF for maximum gain and F is the sample frequency
in Hz. Table 2 illustrates the maximum and minimum
input impedance at different frequencies.
SAMPLING
FREQUENCY
(MHz)
IMPEDANCE
(M) MIN
GAIN
IMPEDANCE
(K) MAX
GAIN
0.5 6.6 208
1 3.3 104
2 1.6 52
4 0.8 26
Table 2 Effects of Frequency on Input Impedance
Calibration
To achieve optimum performance of the WM8143-12, a
calibration procedure must be implemented. This is
achieved by using a combination of the gain and offset
functions to amplify and shift the input signal so that it
lies within and maximises the input ADC range.
Production Data
Wolfson Microelectronics
12
PD. Rev 4 Nov. 99

12 Page





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