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PDF WM8141 Data sheet ( Hoja de datos )
| Número de pieza | WM8141 | |
| Descripción | 12-bit 6MSPS CIS/CCD Analogue Front End/Digitiser | |
| Fabricantes | Wolfson Microelectronics plc | |
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WM8141
12-bit 6MSPS CIS/CCD Analogue Front End/Digitiser
Production Data, October 2000, Rev 3.0
DESCRIPTION
The WM8141 is a 12-bit analogue front end/digitiser that
processes and digitises the analogue output signals from
CCDs or Contact Image Sensors (CIS). The device can be
operated as either a three channel or a single channel
device at pixel sample rates of up to 6MSPS. The device
has both external and programmable internal black level
reference options for CIS operation. The WM8141 runs off a
single supply voltage of either 3.3V or 5V. Alternatively, the
device can be operated from split 5V core and 3.3V digital
interface supplies.
The WM8141 includes three analogue signal processing
channels each of which contains reset level clamping,
correlated double sampling and programmable offset and
gain adjust facilities. Each of these channels is time
multiplexed into a single high-speed 12-bit resolution ADC,
which digitises the pixel image information. The digital data
output is available to the user in either 12-bit parallel or
8/6/4-bit wide multiplexed formats.
The internal control registers are programmable via a
convenient serial or parallel digital interface. The WM8141
typically consumes only 45mA and less than 10µA when in
power down mode.
FEATURES
• 12-bit resolution ADC
• 6MSPS conversion rate at 5V supply
• 5V or 3.3V single supply or 5V/3.3V dual supply operation
• Single or 3 channel operation
• Correlated double sampling
• Programmable gain (8-bit resolution)
• Programmable offset adjust (8-bit resolution)
• 12-bit parallel or 8/6/4-bit wide multiplexed output bus
• Internally generated voltage references
• External or internal reference for CIS operation
• Low power – 225mW typical at 5V supply
• Interface and timing compatible with WM8143, WM8144
and WM8142 devices
• Drop in replacement for WM8143-12
• 32-pin TQFP package
APPLICATIONS
• Flatbed and sheetfeed scanners
• USB compatible scanners
• Multi-function peripherals
• CCD sensor interface
• Contact image sensor (CIS) interface
BLOCK DIAGRAM
VRLC/VBIAS
(18)
VSMP MCLK
(27) (28)
AVDD DVDD1 DVDD2
(12) (14) (32)
VRT VRX VRB
(16) (17) (15)
RINP (21)
GINP (20)
BINP (19)
CL
RLC
RLC
RS
M
U
X
VS TIMING CONTROL
CDS
RM
GU
X
B
8
OFFSET
DAC
+ PGA
VREF/BIAS
RM
GU
X
B
I/P SIGNAL
8 POLARITY
ADJUST
CDS
+ PGA
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
+
M
+U
X
WM8141
(22) OEB
12
BIT
ADC
DATA
I/O
PORT
(30) OP[0]
(31) OP[1]
(1) OP[2]
(2) OP[3]
(3) OP[4]
(4) OP[5]
(5) OP[6]
(6) OP[7]
(7) OP[8]
(8) OP[9]
(9) OP[10]
(10) OP[11]/SDO
RLC
RLC 4
DAC
CDS
+ PGA
+
8 OFFSET
DAC
8 I/P SIGNAL
POLARITY
ADJUST
CONFIGURABLE
SERIAL/
PARALLEL
CONTROL
INTERFACE
(23) SEN/STB
(25) SCK/RNW
(24) SDI/DNA
(26) RLC/ACYC
(11) NRESET
(13)
AGND
(29)
DGND
WOLFSON MICROELECTRONICS LTD
Lutton Court, Bernard Terrace, Edinburgh, EH8 9NX, UK
Tel: +44 (0) 131 667 9386
Fax: +44 (0) 131 667 5176
Email: [email protected]
http://www.wolfson.co.uk
Production Data Datasheets contain final
specifications current on publication date.
Supply of products conforms to Wolfson
Microelectronics’ Terms and Conditions.
2000 Wolfson Microelectronics Ltd.
1 page  
Production Data
WM8141
Test Conditions
AVDD = DVDD1 = DVDD2 = 4.75 to 5.25V, AGND = DGND = 0V, TA = 0 to 70°C, MCLK = 12MHz unless otherwise stated.
PARAMETER
SYMBOL
VRLC/Reset-Level Clamp (RLC)
RLC switching impedance
VRLC short-circuit current
VRLC output resistance
VRLC Hi-Z leakage current
RLCDAC resolution
RLCDAC step size, RLCDAC = 0
VRLCSTEP
RLCDAC step size, RLCDAC = 1
VRLCSTEP
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 0
VRLCBOT
RLCDAC output voltage at
code 0(hex), RLCDACRNG = 1
VRLCBOT
RLCDAC output voltage at
code F(hex) RLCDACRNG, = 0
VRLCTOP
RLCDAC output voltage at
code F(hex), RLCDACRNG = 1
VRLCTOP
Offset DAC, Monotonicity Guaranteed
Resolution
Differential non-linearity
DNL
Integral non-linearity
INL
Step size
Output voltage
Programmable Gain Amplifier
Resolution
Gain
TEST
CONDITIONS
Code 00(hex)
Code FF(hex)
MIN TYP MAX
50
5
2
4
0.24
0.16
0.4
0.25
4.2
2.85
1
8
0.1
0.25
2.04
-260
+260
8
208
283 − PGA[7 : 0]
0.5
1
Max gain, each channel
Min gain, each channel
Gain error, each channel
Supply Currents
Total supply current – active
Total analogue supply current –
active
Digital logic supply current,
DVDD1 – active
Digital I/O supply current,
DVDD2 – active
Supply current – full power down
mode
GMAX
GMIN
IAVDD
7.4
0.74
1
45
42
2
1
10
5
65
Notes: 1. Full-scale input voltage denotes the maximum amplitude of the input signal at the specified gain.
2. Input signal limits are the limits within which the full-scale input voltage signal must lie.
UNIT
Ω
mA
Ω
µA
bits
V/step
V/step
V
V
V
V
bits
LSB
LSB
mV/step
mV
mV
bits
V/V
V/V
V/V
%
mA
mA
mA
mA
µA
WOLFSON MICROELECTRONICS LTD
PD Rev 3.0 October 2000
5
5 Page 
Production Data
WM8141
DEVICE DESCRIPTION
INTRODUCTION
A block diagram of the device showing the signal path is presented on Page 1.
The WM8141 samples up to three inputs (RINP, GINP and BINP) simultaneously. The device then
processes the sampled video signal with respect to the video reset level or an internally/externally
generated reference level using either one or three processing channels.
Each processing channel consists of an Input Sampling block with optional Reset Level Clamping
(RLC) and Correlated Double Sampling (CDS), an 8-bit programmable offset DAC and an 8-bit
Programmable Gain Amplifier (PGA).
The ADC then converts each resulting analogue signal to a 12-bit digital word. The digital output from
the ADC is presented on a 12-bit wide bi-directional bus, with optional 8+4-bit, 6+6-bit or 4+4+4-bit
multiplexed formats.
On-chip control registers determine the configuration of the device, including the offsets and gains
applied to each channel. These registers are programmable via serial or parallel interfaces.
INPUT SAMPLING
The WM8141 can sample and process one to three inputs through one or three processing channels
as follows:
Colour Pixel-by-Pixel: The three inputs (RINP, GINP and BINP) are simultaneously sampled for
each pixel and a separate channel processes each input. The signals are then multiplexed into the
ADC, which converts all three inputs within the pixel period.
Monochrome: A single chosen input (RINP, GINP, or BINP) is sampled, processed by the
corresponding channel, and converted by the ADC. The choice of input and channel can be changed
via the control interface, e.g. on a line-by-line basis if required.
Colour Line-by-Line: A single chosen input (RINP, GINP, or BINP) is sampled and multiplexed into
the red channel for processing before being converted by the ADC. The input selected can be
switched in turn (RINP → GINP → BINP → RINP…) together with the PGA and Offset DAC control
registers by pulsing the RLC/ACYC pin. This is known as auto-cycling. Alternatively, other sampling
sequences can be generated via the control registers. This mode causes the blue and green
channels to be powered down. Refer to the Line-by-Line Operation section for more details.
RESET LEVEL CLAMPING (RLC)
To ensure that the signal applied to the WM8141 lies within its input range (0V to AVDD) the CCD
output signal is usually level shifted by coupling through a capacitor, CIN. The RLC circuit clamps the
WM8141 side of this capacitor to a suitable voltage during the CCD reset level.
A typical input configuration is shown in Figure 5. A clamp pulse, CL, is generated from MCLK and
VSMP by the Timing Control Block. When CL is active the voltage on the WM8141 side of CIN, at
RINP, is forced to the VRLC/VBIAS voltage (VVRLC ) by switch 1. When the CL pulse turns off, the
voltage at RINP initially remains at VVRLC but any subsequent variation in sensor voltage (from reset
to video level) will couple through CIN to RINP.
RLC is compatible with both CDS and non-CDS operating modes, as selected by switch 2. Refer to
the CDS/non-CDS Processing section.
WOLFSON MICROELECTRONICS LTD
PD Rev 3.0 October 2000
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet WM8141.PDF ] | |
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