Datenblatt-pdf.com


WEDPNF8M721V-1012BI Schematic ( PDF Datasheet ) - ETC

Teilenummer WEDPNF8M721V-1012BI
Beschreibung 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip Package
Hersteller ETC
Logo ETC Logo 




Gesamt 42 Seiten
WEDPNF8M721V-1012BI Datasheet, Funktion
White Electronic Designs WEDPNF8M721V-XBX
8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module
Multi-Chip Package ADVANCED*
FEATURES
n Sector Architecture
n Package:
• 275 Plastic Ball Grid Array (PBGA), 32mm x 25mm
n Commercial, Industrial and Military Temperature Ranges
n Weight:
• WEDPNF8M721V-XBX - 2.5 grams typical
• One 16KByte, two 8KBytes, one 32KByte, and fif
teen 64KBytes in byte mode
• One 8K word, two 4K words, one 16K word, and
fifteen 32K word sectors in word mode.
• Any combination of sectors can be concurrently
erased. Also supports full chip erase
SDRAM PERFORMANCE FEATURES
n Organized as 8M x 72
n High Frequency = 100, 125MHz
n Single 3.3V ±0.3V power supply
n Fully Synchronous; all signals registered on positive
edge of system clock cycle
n Boot Code Sector Architecture (Bottom)
n Embedded Erase and Program Algorithms
n Erase Suspend/Resume
• Supports reading data from or programing data to a
sector not being erased
BENEFITS
n Internal pipelined operation; column address can be
changed every clock cycle
n Internal banks for hiding row access/precharge
n Programmable Burst length 1,2,4,8 or full page
n 4096 refresh cycles
FLASH PERFORMANCE FEATURES
n User Configurable as 1Mx8 or 512Kx16
n Access Times of 100, 120, 150ns
n 3.3 Volt for Read and Write Operations
n 1,000,000 Erase/Program Cycles
n 42% SPACE SAVINGS
n Reduced part count
n Reduced I/O count
• 14% I/O Reduction
n Suitable for hi-reliability applications
n SDRAM Upgradeable to 16M x 72 density (contact
factory for information)
n Flash upgradeable to 2M x 8 (or 1M x 16 or 512K x 32)
density
* This data sheet describes a product that may or may not be under
development and is subject to change or cancellation without notice.
September 2002 Rev. 3
1 White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com






WEDPNF8M721V-1012BI Datasheet, Funktion
White Electronic Designs WEDPNF8M721V-XBX
ABSOLUTE MAXIMUM RATINGS
Parameter
Unit
Supply Voltage Range (VCC)
-0.5 to +4.0
V
Signal Voltage Range
-0.5 to Vcc +0.5 V
Operating Temperature TA (Mil)
-55 to +125
°C
Operating Temperature TA (Ind)
-40 to +85
°C
Storage Temperature, Plastic
-65 to +150
°C
Flash Endurance (write/erase cycles)
1,000,000 min. cycles
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions greater than those
indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may
affect reliability.
SDRAM CAPACITANCE (NOTE 2)
Parameter
Input Capacitance: CLK
Addresses, BA0-1 Input Capacitance
InputCapacitance:Allotherinput-onlypins
Input/Output Capacitance: I/Os
Symbol
CI1
CA
CI2
CIO
Max
10
35
10
12
Unit
pF
pF
pF
pF
FLASH DATA RETENTION
Parameter
Minimum Pattern Data
Retention Time
Test Conditions
150°C
125°C
Min
10
20
Unit
Years
Years
DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS (NOTES 1, 3)
(VCC = +3.3V ±0.3V; TA = -55°C TO +125°C)
Parameter/Condition
Supply Voltage
Input High Voltage: Logic 1; All inputs (4)
Input Low Voltage: Logic 0; All inputs (4)
SDRAM
Input Leakage Current: Any input 0V VIN VCC
(All other pins not under test = 0V)
SDRAM Input Leakage Address Current
(All other pins not under test = 0V)
SDRAM Output Leakage Current: I/Os are disabled; 0V VOUT VCC
SDRAM Output High Voltage (IOUT = -4mA)
SDRAM Output Low Voltage (IOUT = 4mA)
Flash
Flash Input Leakage Current (VCC = 3.6, VIN = GND or VCC)
Flash Output Leakage Current (VCC = 3.6, VIN = GND or VCC)
Flash Output High Voltage (IOH = -2.0 mA, VCC = 3.0)
Symbol
VCC
VIH
VIL
II
II
IOZ
VOH
VOL
ILI
ILOx8
VOH1
Min
3
0.7 x Vcc
-0.3
-5
-25
-5
2.4
0.85 X VCC
Max
3.6
VCC + 0.3
0.8
5
25
5
0.4
10
10
Units
V
V
V
µA
µA
µA
V
V
µA
µA
V
Flash Output Low Voltage (IOL = 5.8 mA, VCC = 3.0)
VOL
0.45 V
Flash Low VCC Lock-Out Voltage (5)
VLKO
2.3
2.5 V
NOTES:
1. All voltages referenced to VSS.
2. This parameter is not tested but guaranteed by design. f = 1 MHz, TA = 25°C.
3. An initial pause of 100ms is required after power-up, followed by two AUTO REFRESH commands, before proper device operation is ensured. (VCC must be
powered up simultaneously.) The two AUTO REFRESH command wake-ups should be repeated any time the tREF refresh requirement is exceeded.
4. VIH overshoot: VIH (MAX) = VCC + 2V for a pulse width 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width 3ns.
5. Guaranteed by design, but not tested.
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
6

6 Page









WEDPNF8M721V-1012BI pdf, datenblatt
White Electronic Designs WEDPNF8M721V-XBX
PRECHARGE
The PRECHARGE command is used to deactivate the open
row in a particular bank or the open row in all banks. The
bank(s) will be available for a subsequent row access a
specified time (tRP) after the PRECHARGE command is is-
sued. Input A10 determines whether one or all banks are
to be precharged, and in the case where only one bank is
to be precharged, inputs BA0, BA1 select the bank. Other-
wise BA0, BA1 are treated as “Don’t Care.” Once a bank
has been precharged, it is in the idle state and must be
activated prior to any READ or WRITE commands being is-
sued to that bank.
AUTO PRECHARGE
AUTO PRECHARGE is a feature which performs the same
individual-bank PRECHARGE function described above,
without requiring an explicit command. This is accomplished
by using A10 to enable AUTO PRECHARGE in conjunction
with a specific READ or WRITE command. A precharge of
the bank/row that is addressed with the READ or WRITE com-
mand is automatically performed upon completion of the
READ or WRITE burst, except in the full-page burst mode,
where AUTO PRECHARGE does not apply. AUTO
PRECHARGE is nonpersistent in that it is either enabled or
disabled for each individual READ or WRITE command.
AUTO PRECHARGE ensures that the precharge is initiated at
the earliest valid stage within a burst. The user must not issue
another command to the same bank until the precharge time
(tRP) is completed. This is determined as if an explicit
PRECHARGE command was issued at the earliest possible time.
BURST TERMINATE
The BURST TERMINATE command is used to truncate either
fixed-length or full-page bursts. The most recently registered
READ or WRITE command prior to the BURST TERMINATE
command will be truncated.
AUTO REFRESH
AUTO REFRESH is used during normal operation of the SDRAM
and is analagous to CAS-BEFORE-RAS (CBR) REFRESH in con-
ventional DRAMs. This command is nonpersistent, so it must
be issued each time a refresh is required.
The addressing is generated by the internal refresh control-
ler. This makes the address bits “Don’t Care” during an AUTO
REFRESH command. Each 128Mb SDRAM requires 4,096
AUTO REFRESH cycles every refresh period (tREF). Provid-
ing a distributed AUTO REFRESH command will meet the
refresh requirement and ensure that each row is refreshed.
Alternatively, 4,096 AUTO REFRESH commands can be is-
sued in a burst at the minimum cycle rate (tRC), once every
refresh period (tREF).
SELF REFRESH*
The SELF REFRESH command can be used to retain data in
the SDRAM, even if the rest of the system is powered down.
When in the self refresh mode, the SDRAM retains data with-
out external clocking. The SELF REFRESH command is initi-
ated like an AUTO REFRESH command except CKE is dis-
abled (LOW). Once the SELF REFRESH command is regis-
tered, all the inputs to the SDRAM become “Don’t Care,”
with the exception of CKE, which must remain LOW.
Once self refresh mode is engaged, the SDRAM provides
its own internal clocking, causing it to perform its own AUTO
REFRESH cycles. The SDRAM must remain in self refresh
mode for a minimum period equal to tRAS and may remain
in self refresh mode for an indefinite period beyond that.
The procedure for exiting self refresh requires a sequence
of commands. First, CLK must be stable (stable clock is
defined as a signal cycling within timing constraints speci-
fied for the clock pin) prior to CKE going back HIGH. Once
CKE is HIGH, the SDRAM must have NOP commands is-
sued (a minimum of two clocks) for tXSR, because time is
required for the completion of any internal refresh in
progress.
Upon exiting the self refresh mode, AUTO REFRESH com-
mands must be issued as both SELF REFRESH and AUTO
REFRESH utilize the row refresh counter.
*Self refresh available in commercial and industrial temperatures only.
FLASH DESCRIPTION
The 8Mbit 3.3 volt-only Flash memory is organized as
1,048,576 bytes. The byte-wide (x8) data appears on FD0-
7; the word-wide (x16) data appears on FD0-15. This de-
vice requires only a single 3.3 volt Vcc supply to perform
read, program, and erase operations. A standard EPROM
programmer can also be used to program and erase the
device.
This device features unlock bypass programming and in-
system sector protection/unprotection.
This device offers access times of 100, 120 and 150ns, al-
lowing operation without wait states. To eliminate bus con-
tention the device has separate chip select (FCS), wite en-
able (FWE) and output enable (FOE) controls.
The device requires only a single 3.3 volt power supply for
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
12

12 Page





SeitenGesamt 42 Seiten
PDF Download[ WEDPNF8M721V-1012BI Schematic.PDF ]

Link teilen




Besondere Datenblatt

TeilenummerBeschreibungHersteller
WEDPNF8M721V-1012BC8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip PackageETC
ETC
WEDPNF8M721V-1012BI8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip PackageETC
ETC
WEDPNF8M721V-1012BM8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module Multi-Chip PackageETC
ETC

TeilenummerBeschreibungHersteller
CD40175BC

Hex D-Type Flip-Flop / Quad D-Type Flip-Flop.

Fairchild Semiconductor
Fairchild Semiconductor
KTD1146

EPITAXIAL PLANAR NPN TRANSISTOR.

KEC
KEC


www.Datenblatt-PDF.com       |      2020       |      Kontakt     |      Suche