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Teilenummer | W986416CH |
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Beschreibung | 1M x 16 BIT x 4 BANKS SDRAM | |
Hersteller | Winbond | |
Logo | ||
Gesamt 42 Seiten W986416CH
Features
• 3.3V±0.3V power supply
• Up to 166 MHz clock frequency
• 1,048,576 words x 4 banks x 16 bits organization
• Auto Refresh and Self Refresh
• CAS latency: 2 and 3
• Burst Length: 1, 2, 4, 8 , and full page
• Burst read, Single Writes Mode
• Byte data controlled by UDQM and LDQM
• Power-Down Mode
• Auto-Precharge and controlled precharge
• 4k refresh cycles / 64ms
• Interface: LVTTL
• Package: TSOP II 54 pin, 400 mil - 0.80
1M x 16 bit x 4 Banks SDRAM
General Description
W986416CH is a high speed synchronous dynamic random access memory (SDRAM), organized as 1M words x 4 banks x
16 bits. Using pipelined architecture and 0.20um process technology, W986416CH delivers a data bandwidth of up to 332M
bytes per second (-6). For different application, W986416CH is sorted into four speed grades: -6, -7, -75 and -8H. The -6 parts
can run up to 166Mhz/CL3. The -7 parts can run up to 143Mhz/CL3 specification. The -75 parts can run up to PC133/CL3
specification. The -8H parts can run up to 125Mhz/CL3 or PC100/CL2 specification.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated
by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock
cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst
to maximize its performance. W986416CH is ideal for main memory in high performance applications.
Key Parameters
Symbol
Description
tCK Clock Cycle Time
tAC Access Time from CLK
tRP Precharge to Active Command
tRCD Active to Read/Write Command
ICC1 Operation Current ( Single bank )
ICC4 Burst Operation Current
ICC6 Self-Refresh Current
min/max
min
max
min
min
max
max
max
-6
6ns
5ns
18ns
18ns
80mA
130mA
1mA
-7
7ns
5.4ns
20ns
20ns
65mA
115mA
1mA
-75(PC133)
7.5ns
5.4ns
20ns
20ns
65mA
115mA
1mA
-8H(PC100)
8ns
6ns
20ns
20ns
60mA
110mA
1mA
Revision 1.2
Publication Release Date: June, 1999
-1-
W986416CH
1M x 16 bit x 4 Banks SDRAM
AC CHARACTERISTICS AND OPERATING CONDITION
(Vcc=3.3V±0.3V, Ta=0° to 70°C Notes:5, 6, 7, 8)
SYMBOL
tRC
tRAS
tRCD
tCCD
tRP
tRRD
tWR
tCK
tCH
tCL
tAC
tOH
tHZ
tLZ
tSB
tT
tDS
tDH
tAS
tAH
tCKS
tCKH
tCMS
tCMH
tREF
tRSC
PARAMETER
Ref/Active to Ref/Active Command Period
Active to precharge Command Period
Active to Read/Write Command Delay Time
Read/Write(a) to Read/Write(b)Command
Precharge to Active Command Period
Active(a) to Active(b) Command Period
Write Recovery Time
CL*=2
CL*=3
CLK Cycle Time
CL*=2
CL*=3
CLK High Level width
CLK Low Level width
Access Time from CLK
CL*=2
CL*=3
Output Data Hold Time
Output Data High Impedance Time
Output Data Low Impedance Time
Power Down Mode Entry Time
Transition Time of CLK (Rise and Fall)
Data-in Set-up Time
Data-in Hold Time
Address Set-up Time
Address Hold Time
CKE Set-up Time
CKE Hold Time
Command Set-up Time
Command Hold Time
Refresh Time
Mode register Set Cycle Time
-6
MIN MAX
60
42 10000
18
1
18
12
10
6
10 1000
6 1000
2.5
2.5
6
5
2
26
0
06
0.3 10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
12
-7
MIN MAX
63
42 10000
20
1
20
14
10
7
10 1000
7 1000
2.5
2.5
6
5.4
2.5
2.5 7
0
07
0.3 10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
14
-75(PC133)
MIN MAX
65
45 10000
20
1
20
15
10
7.5
10 1000
7.5 1000
2.5
2.5
6
5.4
2.7
2.7 7.5
0
0 7.5
0.3 10
1.5
0.8
1.5
0.8
1.5
0.8
1.5
0.8
64
15
-8H(PC100)
MIN MAX
68
48 10000
20
1
20
20
10
8
10 1000
8 1000
3
3
6
6
3
38
0
08
0.5 10
2
1
2
1
2
1
2
1
64
16
UNIT
Ns
Cycle
ns
ms
ns
* CL=CAS Latency
Revision 1.2
Publication Release Date: June, 1999
-6-
6 Page W986416CH
1M x 16 bit x 4 Banks SDRAM
Table 2 Address Sequence of Sequential Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Access Address
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
Burst Length
BL= 2 (disturb address is A0)
No address carry from A0 to A1
BL= 4 (disturb addresses are A0 and A1)
No address carry from A1 to A2
BL= 8 (disturb addresses are A0, A1 and A2)
No address carry from A2 to A3
. Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address which is input to the
device. The disturb address is varied by the Burst Length as shown in Table 2.
. Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit in the
sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Access Address
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
A8 A7 A6 A5 A4 A3 A2 A1 A0
Burst Length
BL = 2
BL = 4
BL = 8
Revision 1.2
- 12 -
Publication Release Date: June, 1999
12 Page | ||
Seiten | Gesamt 42 Seiten | |
PDF Download | [ W986416CH Schematic.PDF ] |
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