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PDF W986408CH Data sheet ( Hoja de datos )
| Número de pieza | W986408CH | |
| Descripción | 2M x 8BIT x 4 BANKS SDRAM | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W986408CH
Features
• 3.3V ± 0.3V power supply
• Up to 133MHz clock frequency
• 2,097,152 words x 4 banks x 8 bits organization
• Auto Refresh and Self Refresh
• CAS latency: 2 and 3
• Burst Length: 1, 2, 4, 8 , and full page
• Burst read, Single Writes Mode
• Byte data controlled by DQM
• Power-Down Mode
• Auto-Precharge and controlled precharge
• 4k refresh cycles / 64ms
• Interface: LVTTL
• Package: TSOP II 54 pin, 400 mil - 0.80
2M x 8 bit x 4 Banks SDRAM
General Description
W986408CH is a high speed synchronous dynamic random access memory (SDRAM) , organized as 2M words x 4 banks x
8 bits. Using pipelined architecture and 0.20um process technology, W986408CH delivers a data bandwidth of up to 133M ( -
75) bytes per second. To fully comply to the personal computer industrial standard, W986408CH is sorted into two speed
grades: -75 and -8H. The -75 is compliant to the PC133 specitication, The -8H is compliant to the PC100/CL2 specification
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be accessed at a burst length of
1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE command. Column addresses are automatically generated
by the SDRAM internal counter in burst operation. Random column read is also possible by providing its address at each clock
cycle. The multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle, interleave or sequential burst
to maximize its performance. W986408CH is ideal for main memory in high performance applications.
Key Parameters
Symbol
Description
tCK Clock Cycle Time
tAC Access Time from CLK
tRP Precharge to Active Command
tRCD Active to Read/Write Command
ICC1 Operation Current ( Single bank )
ICC4 Burst Operation Current
ICC6 Self-Refresh Current
min/max
min
max
min
min
max
max
max
-75 (PC133)
7.5ns
5.4ns
20ns
20ns
65mA
115mA
1mA
-8H (PC100)
8ns
6ns
20ns
20ns
60mA
110mA
1mA
Revision 1.0
Publication Release Date: March, 1999
-1-
1 page  
W986408CH
ABSOLUTE MAXIMUM RATINGS
SYMBOL
ITEM
VIN,VOUT
Input, Output Voltage
VCC,VCCQ
Power Supply Voltage
TOPR
Operating Temperature
TSTG
Storage Temperature
TSOLDER
Soldering Temperature(10s)
PD Power Dissipation
IOUT Short Circuit Output Current
2M x 8 bit x 4 Banks SDRAM
RATING
-0.3~VCC+0.3
-0.3~4.6
0~70
-55~150
260
1
50
UNIT
V
V
°C
°C
°C
W
mA
NOTES
1
1
1
1
1
1
1
RECOMMENDED DC OPERATING CONDITIONS ( Ta = 0 to 70°C )
SYMBOL
PARAMETER
MIN TYP
MAX
UNIT
VCC Power Supply Voltage
3.0 3.3
3.6
V
VCCQ
Power Supply Voltage (for I/O Buffer)
3.0
3.3
3.6
V
VIH Input High Voltage
2.0
-
VCC+0.3
V
VIL Input Low Voltage
-0.3 -
0.8 V
Note: VIH(max) = VCC/VCCQ+1.2V for pulse width < 5ns
VIL(min) = VSS/VSSQ-1.2V for pulse width < 5ns
NOTES
2
2
2
2
CAPACITANCE (VCC=3.3V, f = 1MHz, Ta=25°C)
SYMBOL
PARAMETER
Input Capacitance (A0 to A11, BS0 ,BS1, CS, RAS, CAS, WE, DQM, CKE)
CI
Input Capacitance (CLK)
CO Input/Output capacitance
Note: These parameters are periodically sampled and not 100% tested.
MIN MAX UNIT
- 4 pf
- 4 pf
- 6.5 pf
Revision 1.0
Publication Release Date: March, 1999
-5-
5 Page 
W986408CH
2M x 8 bit x 4 Banks SDRAM
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The Mode Register sets type of burst
(sequential or interleave) and the burst length (1, 2, 4, 8, full page) during the Mode Register Set cycle. Table 2 and 3 on the
next page explain the address sequence of interleave mode and sequential mode.
Burst Write Command
The Burst Write command is initiated by applying logic low level to CS, CAS and WE while holding RAS high at the rising
edge of the clock. The address inputs determine the starting column address. Data for the first burst write cycle must be applied
on the DQ pins on the same clock cycle that the Write Command is issued. The remaining data inputs must be supplied on each
subsequent rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes will be
ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted, the remaining addresses
are overridden by the new read address with the full burst length. The data from the first Read Command continues to appear on
the outputs until the CAS latency from the interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output drivers) in a high impedance
state to avoid data contention on the DQ bus. If a Read Command will issue data on the first and second clocks cycles of the
write operation, DQM is needed to insure the DQs are tri-stated. After that point the Write Command will have control of the
DQ bus and DQM masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the previous burst is
interrupted, the remaining addresses are overridden by the new address and data will be written into the device until the
programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read Command is activated. The DQs
must be in the high impedance state at least one cycle before the new read data appears on the outputs to avoid data contention.
When the Read Command is activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank open for future Read or Write
Commands to the same page of the active bank, if the burst length is full page. Use of the Burst Stop Command during other burst
length operations is illegal. The Burst Stop Command is defined by having RAS and CAS high with CS and WE low at the rising
edge of the clock. The data DQs go to a high impedance state after a delay which is equal to the CAS Latency in a burst read
cycle interrupted by Burst Stop. If a Burst Stop Command is issued during a full page burst write operation, then any residual data
from the burst write cycle will be ignored.
Revision 1.0
- 11 -
Publication Release Date: March, 1999
11 Page | ||
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