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PDF W981616BH Data sheet ( Hoja de datos )
| Número de pieza | W981616BH | |
| Descripción | 512K 2 BANKS 16 BITS SDRAM | |
| Fabricantes | Winbond | |
| Logotipo |  |
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W981616BH
512K × 2 BANKS × 16 BITS SDRAM
GENERAL DESCRIPTION
W981616BH is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words × 2 banks × 16 bits. Using pipelined architecture and 0.175 µm process technology,
W981616BH delivers a data bandwidth of up to 332M bytes per second (-5). For different applications
the W981616BH is sorted into the following speed grades: -5, -6, and –7(L).
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W981616BH is ideal for main memory in
high performance applications.
FEATURES
• 3.3V ±0.3V power supply
• Up to 166 MHz clock frequency
• 524,288 words x 2 banks x 16 bits organization
• Auto Refresh and Self Refresh
• CAS latency: 2 and 3
• Burst Length: 1, 2, 4, 8, and full page
• Burst read, Single Write Mode
• Byte data controlled by UDQM and LDQM
• Auto-precharge and controlled precharge
• 4K refresh cycles/64 mS
• Interface: LVTTL
• Packaged in 50-pin, 400 mil TSOP II
PIN CONFIGURATION
VCC
DQ0
DQ1
VSS Q
DQ2
DQ3
VCCQ
DQ4
DQ5
VSS Q
DQ6
DQ7
VCCQ
LDQM
WE
CAS
RAS
CS
BA
A10
A0
A1
A2
A3
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
50 VSS
49 DQ15
48 DQ14
47 VSS Q
46 DQ13
45 DQ12
44 VCCQ
43 DQ11
42 DQ10
41 VSS Q
40 DQ9
39 DQ8
38 VCCQ
37 NC
36 UDQM
35 CLK
34 CKE
33 NC
32 A9
31 A8
30 A7
29 A6
28 A5
27 A4
26 VSS
Publication Release Date: February 2000
- 1 - Revision A2
1 page  
W981616BH
Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding
RAS and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8, full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
Burst Write Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding RAS high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS latency from the
interrupting Read Command the is satisfied.
Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When
the previous burst is interrupted, the remaining addresses are overridden by the new address and
data will be written into the device until the programmed burst length is satisfied.
Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is
full page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst
Publication Release Date: February 2000
- 5 - Revision A2
5 Page 
W981616BH
DC CHARACTERISTICS
(VCC = 3.3V ±0.3V, TA = 0°~70°C)
PARAMETER
Operating Current
tCK = min., tRC = min.
Active precharge command
cycling without burst
operation
1 bank operation
Standby Current
CKE = VIH
tCK = min., CS = VIH
VIH /L = VIH (min.) /VIL
(max.)
Bank: inactive state
CKE = VIL
(Power down mode)
Standby Current
CKE = VIH
CLK = VIL, CS = VIH
VIH/L = VIH (min.) /VIL (max.)
Bank: inactive state
CKE = VIL
(Power down mode)
No Operating Current
CKE = VIH
tCK = min., CS = VIH (min.)
Bank: active state (2 banks)
CKE = VIL
(Power Down mode)
Burst Operating Current
(tCK = min.)
Read/ Write command cycling
Auto Refresh Current
(tCK = min.)
Auto refresh command cycling
Self Refresh Current
(CKE = 0.2V)
Self refresh mode
SYM
.
ICC1
-5
MAX.
100
-6
MAX.
90
ICC2
45
35
ICC2P
ICC2S
1
8
1
8
ICC2P
S
ICC3
1
55
1
50
ICC3P
3
ICC4 190
ICC5 125
ICC6
1
3
165
120
1
-7
MAX.
80
-7L
MAX.
80
30 30
11
88
11
45 45
33
145 145
110 110
1 0.45
UNIT NOTES
3
3
3
mA
3, 4
3
PARAMETER
Input Leakage Current
(0V ≤ VIN ≤ VCC, all other pins not under test = 0V)
Output Leakage Current
(Output disable , 0V ≤ VOUT ≤ VCCQ )
LVTTL OutputT ″H″ Level Voltage
(IOUT = -2 mA)
LVTTL Output ″L″ Level Voltage
(IOUT = 2 mA)
SYM.
II(L)
IO(L)
VOH
VOL
MIN.
-5
MAX. UNIT NOTES
5 µA
-5 5 µA
2.4 - V
- 0.4 V
- 11 -
Publication Release Date: February 2000
Revision A2
11 Page | ||
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| PDF Descargar | [ Datasheet W981616BH.PDF ] | |
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