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PCF8820U Schematic ( PDF Datasheet ) - NXP Semiconductors

Teilenummer PCF8820U
Beschreibung 67 x 101 Grey-scale/ECB colour dot matrix LCD driver
Hersteller NXP Semiconductors
Logo NXP Semiconductors Logo 




Gesamt 30 Seiten
PCF8820U Datasheet, Funktion
INTEGRATED CIRCUITS
DATA SHEET
PCF8820
67 × 101 Grey-scale/ECB colour
dot matrix LCD driver
Product specification
File under Integrated Circuits, IC12
2000 Dec 07






PCF8820U Datasheet, Funktion
Philips Semiconductors
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
Product specification
PCF8820
6.2 Pad functions
6.2.1 ROW DRIVER OUTPUTS
Row driver outputs (R0 to R66) are the outputs for the LCD
row drive signals. They should be connected directly to the
67 rows of the LCD. If less than 67 rows are required, the
unused outputs must be left open-circuit.
6.2.2 COLUMN DRIVER OUTPUTS
Column driver outputs (C0 to C100) are the outputs for the
LCD column drive signals. They should be connected
directly to the 101 columns of the LCD. If less than
101 columns are required, the unused column outputs
must be left open-circuit.
6.2.3 GROUND SUPPLY
The ground supply rails (VSS1 and VSS2) must be
connected together. VSS1 is related to VDD1 and VDD3;
VSS2 is related to VDD2.
6.2.4 SUPPLY VOLTAGE
The supply voltage rails (VDD1, VDD2 and VDD3) must be
connected together when the same supply is used for both
the logic circuits and for the voltage multiplier. When the
circuits are fed separately, VDD2 and VDD3 must be
connected to the same supply.
6.2.5 VOLTAGE MULTIPLIER OUTPUT
VLCDOUT is the output of the voltage multiplier of the high
voltage generator.
6.2.6 VOLTAGE MULTIPLIER REGULATION INPUT
VLCDSENSE is the regulation input of the high voltage
multiplier and must be connected to VLCDOUT.
6.2.7 SUPPLY VOLTAGE OF BIAS VOLTAGE GENERATOR
VLCD is the supply voltage on pad VLCDIN for the bias
voltage generator which supplies the LCD outputs. The
voltage on pad VLCDIN must not be lower than VDD1.
If VLCD is generated internally, pad VLCDOUT must be
connected to pad VLCDIN.
If VLCD is supplied externally, the external supply voltage
must be connected to pad VLCDIN. An external supply
voltage must be applied after applying VDD1, and it must be
removed before or when removing VDD1 (see Fig.25). It is
recommended that an external supply voltage is applied
after leaving the reset state. The external supply voltage
can stay applied in the Power-down mode.
When an external supply voltage is used, pads VLCDIN,
VLCDSENSE and VLCDOUT do not have to be connected
together. However, if pads VLCDSENSE and VLCDOUT are
both connected to pad VLCDIN, the current consumption
can be reduced under the following conditions:
The output of VLCDOUT is set to high-impedance
(see Table 8)
The HIGH voltage programming range is selected by
setting bit PRS = 1, the maximum voltage multiplier on
factor 8 and the VLCD control register on the maximum
value (see Table 2).
6.2.8 LCD INTERMEDIATE BIAS VOLTAGES
The LCD intermediate bias voltages (V2, V3, V4 and V5)
which are applied to the LCD columns and rows are
present on these pads for test purposes. They must be left
open-circuit in the application.
6.2.9 SERIAL DATA INPUT
SDA_IN is the serial data input from the I2C-bus.
6.2.10 SERIAL DATA OUTPUT
SDA_OUT is the serial data output (data, acknowledge)
for the I2C-bus. Connecting pad SDA_OUT to
pad SDA_IN makes the SDA line fully I2C-bus compatible.
Not connecting pad SDA_IN to pad SDA_OUT allows the
device to be used in applications in which the acknowledge
bit is not required. In Chip-On-Glass (COG) applications, it
is sometimes beneficial not to connect pad SDA_OUT to
pad SDA_IN. This is because in COG applications where
the track resistance from pad SDA_OUT to the system
SDA line is significant, a voltage divider is created by the
bus pull-up resistor and the Indium Tin Oxide (ITO) track
resistance. This divider could prevent the PCF8820 from
asserting a valid logic 0 level during an acknowledge
cycle.
In COG applications, where the acknowledge cycle is
required, the track resistance from the pad SDA_OUT to
the system SDA line must be minimized to guarantee a
valid LOW-level.
6.2.11 SERIAL CLOCK INPUT
SCL is the serial clock input from the I2C-bus.
2000 Dec 07
6

6 Page









PCF8820U pdf, datenblatt
Philips Semiconductors
67 × 101 Grey-scale/ECB colour dot matrix
LCD driver
Product specification
PCF8820
handbook, full pageLwSidtBh
DB0
P0
MSB
DB1
P0
LSB
DB2
P1
MSB
DB3
P1
LSB
DB4
P2
MSB
DB5
P2
LSB
DB6
P3
MSB
MSB
DB7
P3
LSB
P0
P1
P2
P3
..
.
X
R = row
P = pixel
LSB
P0 bank 0
P1
P2
P3
bank 1
pixel 0
MSB
top of LCD
R0
bank 2
R4
bank 3
R8
R12
.
.
.
.
R16
bank 13 . LCD
bank 14
R52
bank 15
R56
bank 16
R60
R64
X
R66
MGT118
2000 Dec 07
Fig.6 DDRAM to display mapping.
12

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