PDF W89C982AF Data sheet ( Hoja de datos )

Número de pieza	W89C982AF
Descripción	INTEGRATED MULTIPLE REPEATER II
Fabricantes	Winbond
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No Preview Available ! www.DataSheet4U.com Preliminary W89C982AF INTEGRATED MULTIPLE REPEATER II GENERAL DESCRIPTION................................................................................................................. 2 FEATURES........................................................................................................................................ 2 ORDERING INFORMATION.............................................................................................................. 2 SYSTEM DIAGRAM .......................................................................................................................... 3 PIN CONFIGURATION ...................................................................................................................... 3 PIN DESCRIPTION ........................................................................................................................... 4 BLOCK DIAGRAM ............................................................................................................................. 8 FUNCTIONAL DESCRIPTION ........................................................................................................... 8 AUI Interface and Twisted Pair Line Transceiver ..........................................................................................8 Link Test Function.........................................................................................................................................8 Automatic Polarity Reversal Function ...........................................................................................................9 Port Partition/Reconnection Logic.................................................................................................................9 Port Status Direct Report Function ...............................................................................................................9 Initial State After Reset ...............................................................................................................................11 Management Logic and Management Interface .........................................................................................11 IMPR II Programmable Options..................................................................................................................15 The IMPR II Kernel Logic............................................................................................................................15 Inter-IMPR II Interface.................................................................................................................................16 ABSOLUTE MAXIMUM RATINGS ................................................................................................... 17 DC CHARACTERISTICS ................................................................................................................. 17 AC CHARACTERISTICS ................................................................................................................. 19 System Clock Timing..................................................................................................................................19 Reset Timing...............................................................................................................................................19 Management Bus Clock Timing..................................................................................................................20 Management Bus Carrier Sense Timing.....................................................................................................20 Inter-IMPR II Interface Input Timing ............................................................................................................21 Inter-IMPR II Interface Output Timing .........................................................................................................22 Inter-IMPR II Interface Collision Timing.......................................................................................................23 Inter-IMPR II Interface to AUI/TP Port Timing.............................................................................................23 Output Driver Timing...................................................................................................................................24 Repetition Timing (part 1) ...........................................................................................................................24 Repetition Timing (part 2) ...........................................................................................................................25 Link Test Timing..........................................................................................................................................26 PACKAGE DIMENSIONS ................................................................................................................ 28 www.DataSheet4U.com Publication Release Date: November 1996 - 1 - Revision A1 1 page www.DataSheet4U.com Preliminary W89C982AF Continued NAME INTER-IMPR II INTERFACE PINS NO. I/O DESCRIPTION IBEN 39 I Inter-IMPR II interface Enable: IBEN is driven by HUB integrator. The integrator will drive the IBEN low if there is only one IMPR II which outputs ICRS to the inter-IMPR II interface. The IMPR II that asserts ICRS will be allowed to transmit valid messages to the IMPR II integrator when IBEN is low. ICOL 40 I Inter-IMPR II Collision: ICOL will be driven low when more than one IMPR II simultaneously output ICRS to the IMPR II integrator. The IMPR II will not transmit any data to the IMPR II integrator when ICOL is low. On this situation the collision messages will still be sent to all ports of the IMPR II. IDCLK 44 I Inter-IMPR II Data Clock: O IDCLK will drive a 10 MHz clock output when ICRS is asserted and IBEN is driven. If ICRS is not asserted and IBEN is driven, IDCLK will be driven by the IDCLK signal of another IMPR II. If a dumb hub is used, i.e., no IBEN is present, this pin is in high impedance. This pin is synchronous to IDAT data. IDAT 45 I Inter-IMPR II Data: O The IMPR II sends/receives valid packets or inter-port collision Z messages to/from other IMPR IIs through the IDAT pin in NRZ format. IDAT is in high-Z state during inter-IMPR II collisions or when the network is idle. IDAT remains high when there is a transmit collision in the IMPR II. IJAM 42 I Inter-IMPR II IJAM: O IJAM is driven low when a valid packet is being sent. IJAM is driven high when IDAT carries a collision message (i.e., always Z high or always low). IDAT = 0 indicates a multiport collision and IDAT = 1 indicates a single port collision condition. During inter-IMPR II collisions or when the network is idle, IJAM should be in high-Z state. MANAGEMENT BUS PINS RST 38 I IMPR II Reset: The IMPR II will be forced into its initial state when RST is driven low. MCLK 28 I Management Bus Clock: The management data are clocked by MCLK serially. The rising edge of MCLK will latch the data into or out of the IMPR II. www.DataSheet4U.com Publication Release Date: November 1996 - 5 - Revision A1 5 Page www.DataSheet4U.com Preliminary W89C982AF XCOLRPT W89C982AF AUIRPT TP0RPT M1 M0 ..... TP7RPT * Set M1, M0 to select port status output. R R = 330 Collision LED .... R R = 330 TP7 status LED Initial State After Reset When RST is driven low, the IMPR II is reset. The minimum time the reset signal must be held low to trigger a reset is 100 µS. During reset, the IMPR II places all outputs in the inactive state (except for the auto polarity reversal function). Active low outputs stay high, active high outputs stay low, link test is enabled, and the TP link is in a fail state. The AUI/TP auto partition/reconnection uses the standard algorithm, AUI/TP transmitters are idle, AUI/TP receivers are enabled, IDAT and IJAM are in high- impedance state, STR is low, and the auto polarity reversal function is enabled. Management Logic and Management Interface The major functions of the management logic are enabling/disabling networks, partitioning/recon- necting network ports, enabling/disabling the link test and autopolarity reversal functions of the twisted pair line transceiver, and accessing the link status and polarity status of the twisted pair line transceiver. The management interface is a signal bus that contains input/output signals to/from the management logic and the internal carrier sense signals for the nine network ports of the IMPR II. The management logic can accept and execute management commands when the IMPR II is in normal mode, i.e., the TEST pin of the IMPR II is tied low. All management commands are byte- oriented and are clocked into the IMPR II serially by an external clock. Some of the commands require an output from the IMPR II in response and some do not. At least 20 clocks are required to send a command that requires an output response from the IMPR II; 14 clocks are needed to send a command that requires no response. The serial command data stream and any associated output response data stream are structured in a manner compatible with the RS232 serial data format, i.e., one start bit followed by eight data bits, with the LSB sent first and the MSB last. www.DataSheet4U.com - 11 - Publication Release Date: November 1996 Revision A1 11 Page

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