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W89C926 Schematic ( PDF Datasheet ) - Winbond

Teilenummer W89C926
Beschreibung PCMCIA ETHERNET NETWORK TWISTED PAIR INTERFACE CONTROLLER
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W89C926 Datasheet, Funktion
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Preliminary W89C926 PENTIC+
PCMCIA ETHERNET NETWORK
TWISTED PAIR INTERFACE CONTROLLER
GENERAL DESCRIPTION
The W89C926 PENTIC+ is a CMOS device designed for easy implementation of PCMCIA R2.1
compatible CSMA/CD local area networks. The W89C926 combines a W89C902 Serial LAN
Coprocessor for Twisted-pair (SLCT) with a PCMCIA Bus Interface (PBI), thus integrating into
a single chip all the registers and logic necessary to connect the SLCT to buffer SRAMs, flash
memories (or an EEPROM), and the PCMCIA system bus.
The PCMCIA Bus Interface (PBI) is designed to provide a switchless setting architecture that allows
the card setting to be configured by software. It implements a full set of PCMCIA registers for
PCMCIA R2.1 compatibility and a set of configuration registers for switchless card setting. The card
can be configured quickly and easily by modifying the contents of the configuration registers. The
PENTIC+ can run with shared memory mode and NE2000TM I/O mode drivers on a 16-bit bus
interface. No extra effort is needed to ensure software compatibility.
The PENTIC+ provides a flexible flash memory (up to 128 KB)/EEPROM (up to 512 bytes)
architecture for PCMCIA nonvolatile storage and an ID/Configuration auto-load architecture for
power-on initialization. Vendors can store the EthernetID, configuration, and CIS in the flash
memory or EEPROM. The PENTIC+ will auto-load necessary information when power is switched on.
FEATURES
Runs with NE2000 TM or shared memory drivers
Supports up to 128 KB flash memory (8K/112K for attribute/common memory) or 512 bytes
EEPROM (for attribute memory only) for nonvolatile memory
Uses one 16 KB SRAM or one 32 KB SRAM (if EEPROM is used) for 16 KB Ethernet ring buffer
Auto-load algorithm provided for power-on initialization
Supports necessary PCMCIA registers
Configuration registers allow switchless card setting
UTP/BNC auto media-switching function provided
Drives necessary LEDs for network status display
Single 5V power supply with low power consumption
100-pin thin package (TQFP) fits into PCMCIA Type II profile
Ethernetis a registered trademark of the Xerox Corporation.
NE2000TM is a trademark of Novell, Inc.
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-1-
Publication Release Date: January 1996
Revision A1






W89C926 Datasheet, Funktion
www.DataSheet4U.com
W89C926 PENTIC+
Pin Description, continued
NAME
NUMBER
MSWR
86
Network Interface
TXO+, -
60, 59
RXI+, -
58, 57
TX+, -
RX+, -
CD+, -
X1
X2
64, 63
66, 65
68, 67
55
54
THIN
51
ACTLED
52
TYPE
O/TTL
DESCRIPTION
Memory Support Write:
MSWR is asserted by the PENTIC+ to strobe write data
into the on-board memory. Both SRAM and flash
memory use MSWR as the write command strobe.
O/DIF
I/DIF
O/DIF
I/DIF
I/DIF
I/XTAL
O/XTAL
O/TTL
O/TTL
Twisted Pair Transmit Outputs:
UTP differential output pair. A 1.21 Kprecision resistor
should be shunted across these pins for signal pre-
equalization.
Twisted Pair Receive Inputs:
These inputs are fed into a differential amplifier which
passes valid data to the LCE core. A 100precision
resistor should be shunted across these pins for
impedance matching.
AUI Transmit Outputs:
Differential transmit outputs. These pins should be con-
nected to 270 ohm external pull-down resistors.
AUI Receive Inputs:
Differential receive input pair from AUI interface.
AUI Collision Inputs:
Differential collision input pair from AUI interface.
Crystal Input:
Master 20 MHz clock input.
Crystal Feedback Output:
This pin should be connected to the crystal when a
crystal is used and should be left unconnected when an
oscillator is used.
Thin Cable Select:
This pin is high when the PENTIC+ is configured for thin
cable media. It can be used as a switch to DC-DC con-
verter for network media selection.
Activity:
This output asserts low for approximately 50 mS
whenever the PENTIC+ transmits or receives data
without collisions. This output can also be controlled by
the power-down state machine; refer to the descriptions
of the COR and CFA registers for more details.
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-6-

6 Page









W89C926 pdf, datenblatt
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W89C926 PENTIC+
Buffer Memory Mapping
NIC CORE
MEMORY MAP
0000H
001FH
0020H
00FFH
0100H
3FFFH
4000H
7FFFH
8000H
BFFFH
C000H
FFFFH
Nonvolatile Memory Mapping
F/ EE = 1 (flash memory used)
SYSTEM
OFFSET (HA0-16)
00000H
03FFFH
04000H
1FFFFH
NE2000 COMPATIBLE
ID Registers
Aliased
ID Registers
Buffer SRAM
(16K × 8)
Aliased
ID Registers
Aliased Buffer SRAM
MEMORY TYPE
Attribute/
Flash
Common/
Flash
NAME
CIS/ID/PCMCIA Register
(8K × 8)
(112K × 8)
F/ EE = 0 (EEPROM used)
SYSTEM
OFFSET (HA0-16)
MEMORY TYPE
NAME
00000H
Attribute/
CIS
003D6H
(Note)
(492 × 8)
Notes:
1. This attribute memory is an image from EEPROM. It is actually resident in upper half of the SRAM after power-on auto-
loading.
2. Refer to "Attribute Memory Mapping" for detailed locations.
3. The PENTIC+ decodes HA0-16 for memory access. The (common or attribute) MEMBase addresses are left for the host adapter
and the socket service to determine.
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- 12 -

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