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W89C840AF Schematic ( PDF Datasheet ) - Winbond

Teilenummer W89C840AF
Beschreibung 100/10Mbps Ethernet Controller
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W89C840AF Datasheet, Funktion
www.DataSheet4U.com
W89C840AF
Winbond LAN
W89C840AF
100/10Mbps Ethernet Controller
www.DataSheet4U.com
Publication Release Date:October 2000
-1 - Revision 1.01






W89C840AF Datasheet, Funktion
www.DataSheet4U.com
W89C840AF
Pin Descriptions
1) PCI Interface
Signal Name
PCICLK
RSTB
AD[31:0]
C_BEB[3:0]
PAR
FRAMEB
Pin
Type
I
Pin
Number
114
I 112
IO/TS
IO/TS
121-128,
5-12,
27-34,
38-45
3,15,24,
35
IO/TS
23
IO/STS
16
Pin Description
PCI Clock Input:
W89C840AF supports PCI clock rate ranged from
25Mhz to 33MHz continuously. All PCI signals except
RST# and INTA#, are referenced on the rising edge of
this clock.
PCI Hardware reset signal:
When asserted(active low), all PCI output pins of
W89C840AF will be in high impedance state, and all
open drain signals will be floated. The configurations
inside W89C840AF will be in its initial state. This
signal must be asserted for a period of at least 10 PCI
clocks to correctly take effect of a reset on hardware.
PCI Multiplexed Address and Data bus:
During the first cycle that FRAME# asserts, they act as
an address bus; on the other cycles, they are switched to
be a data bus.
Multiplexed command and byte enables:
These signals are driven by current bus master. During
address phase, they mean a bus command; on the other
phase, they present the byte enable of the transaction.
Parity signal.
This PAR represents the even parity across AD[31:0]
and C_BEB[3:0]. It has the same timing as AD[31:0]
but is delayed by one clock.
PCI Cycle Frame:
The current bus master asserts FRAMEB to indicate the
beginning and duration of a bus access. This signal
keeps asserted while the current transaction is ongoing
and keeps deasserted to indicate that the next data
phase is the final data phase.
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Publication Release Date:October 2000
-6 - Revision 1.01

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W89C840AF pdf, datenblatt
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W89C840AF
Register (FWUPCS) and it should be ensure the PME_EN bit is set only when the W89C840AF is in the D3
state.
Below table describes the Wake-Up, Power Management Control and Status registers with EEPROM
bits that control the PMEB signal.
Bit
FPMCSR<8>
PME_EN
FPMCSR<15>
PME_STS
FCS<20>
CAPS
FWUPCS<31>
PMCSP
FWUPCS<30>
RWUL
FWUPCS<0>
MGPE
Location
PCI configuration
space
PCI configuration
space
PCI configuration
space
Descriptin
PME_EN---Power management enable bit set enables the
assertion of the PMEB signal when a PME occurs.
PME_STS---Power management status bit is indicates that a
PME has occurred. When this bit is cleared, the PMEB signal is
deasserted.
CAPS---The value of this bit determines whether the
W89C840AF implements the PCI power management
capabilities. The value of this bit is loaded from EEPROM
08H<15> bit (power management capability support).
PCI configuration
space
PCI configuration
space
RWUL---The value of this bit is loaded from EEPROM 08H<14>
bit (Remote wake-up from LAN). After Hard-Reset, if RWUL=1
and PMCSP=1 the W89C840AF will enable Remote Wake-Up
from LAN mode. While in Remote Wake-Up from LAN mode,
W89C840AF will assert PMEB signal if Magic Packet has been
received. The W89C840AF PMEB signal will remain asserted
during power state changes from D3 (hot) to D0 (un-initialized)
until either bit 15 and/or bit 8 in the FPMCSR is cleared.
MGPE---After Hard-Reset, if RWUL=1 and PMCSP=1 Magic
Packet detector enable bit set to 1 to enable the operation of
Magic Packet detector. This bit is reset when W89C840AF power
state changes from D3 (hot) to D0 (un-initialized).
Magic Packet
While in Remote Wake-Up from LAN mode, the W89C840AF is in low power state (W89C940A all
VDD and pins must remains at their supply levels). The device will not generate any bus master transfers, no
transmit operations will be initiated on the network. it require the received packet match as a Magic Packet,
after which it generates a weak-up signal.
The Magic Packet's packet matches as following rules:
1. The valid destination address that pass of the W89C840AF address filtering machine
2. The received Magic Packet does not contain CRC error.
3. Includes, anywhere in the packet with no breaks sequence of 6 bytes FFh synchronization stream
followed by 16 duplications of the destination address.
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-12 -
Publication Release Date:October 2000
Revision 1.01

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