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W83L517D Schematic ( PDF Datasheet ) - Winbond

Teilenummer W83L517D
Beschreibung LPC SUPER I/O
Hersteller Winbond
Logo Winbond Logo 




Gesamt 30 Seiten
W83L517D Datasheet, Funktion
W83L517D
Version 0.6
WINBOND
LPC SUPER I/O
W83L517D
I






W83L517D Datasheet, Funktion
W83L517D
Version 0.6
6. PARALLEL PORT .............................................................................................. 86
6.1 PRINTER INTERFACE LOGIC.................................................................................................. 86
6.2 ENHANCED PARALLEL PORT (EPP)....................................................................................... 87
6.2.1 Data Swapper ..................................................................................................................... 87
6.2.2 Printer Status Buffer............................................................................................................ 88
6.2.3 Printer Control Latch and Printer Control Swapper............................................................... 89
6.2.4 EPP Address Port ............................................................................................................... 89
6.2.5 EPP Data Port 0-3............................................................................................................... 90
6.2.6 Bit Map of Parallel Port and EPP Registers ......................................................................... 90
6.2.7 EPP Pin Descriptions .......................................................................................................... 91
6.2.8 EPP Operation .................................................................................................................... 91
6.3 EXTENDED CAPABILITIES PARALLEL (ECP) PORT .............................................................. 92
6.3.1 ECP Register and Mode Definitions..................................................................................... 92
6.3.2 Data and ecpAFifo Port ....................................................................................................... 93
6.3.3 Device Status Register (DSR) ............................................................................................. 93
6.3.4 Device Control Register (DCR)............................................................................................ 94
6.3.5 cFifo (Parallel Port Data FIFO) Mode = 010......................................................................... 95
6.3.6 ecpDFifo (ECP Data FIFO) Mode = 011 .............................................................................. 95
6.3.7 tFifo (Test FIFO Mode) Mode = 110 .................................................................................... 95
6.3.8 cnfgA (Configuration Register A) Mode = 111...................................................................... 95
6.3.9 cnfgB (Configuration Register B) Mode = 111...................................................................... 95
6.3.10 ecr (Extended Control Register) Mode = all ....................................................................... 96
6.3.11 Bit Map of ECP Port Registers ........................................................................................ . 97
6.3.12 ECP Pin Descriptions ...................................................................................................... 98
6.3.13 ECP Operation .................................................................................................................. 98
6.3.14 FIFO Operation ................................................................................................................. 99
6.3.15 DMA Transfers .................................................................................................................. 99
6.3.16 Programmed I/O (NON-DMA) Mode .................................................................................. 99
6.4 EXTENSION FDD MODE (EXTFDD)....................................................................................... 100
6.5 EXTENSION 2FDD MODE (EXT2FDD)................................................................................... 100
7. GENERAL PURPOSE I/O ................................................................................ 101
8. ACPI REGISTERS FEATURES......................................................................... 104
IV Publication Release Date: Apr. 2000
Revision 0.60

6 Page









W83L517D pdf, datenblatt
1. PIN DESCRIPTION
Note: Please refer to Section 13.2 DC CHARACTERISTICS for details.
I/O8t - TTL level bi-directional pin with 8 mA source-sink capability
I/O12t - TTL level bi-directional pin with 12 mA source-sink capability
I/O12tp3 - 3.3V TTL level bi-directional pin with 12 mA source-sink capability
I/OD12t - TTL level bi-directional pin open drain output with 12 mA sink capability
I/O24t - TTL level bi-directional pin with 24 mA source-sink capability
OUT12t - TTL level output pin with 12 mA source-sink capability
OUT12tp3 - 3.3V TTL level output pin with 12 mA source-sink capability
OD12 - Open-drain output pin with 12 mA sink capability
OD24 - Open-drain output pin with 24 mA sink capability
INcs
- CMOS level Schmitt-trigger input pin
INt - TTL level input pin
INtd - TTL level input pin with internal pull down resistor
INts - TTL level Schmitt-trigger input pin
INtsp3 - 3.3V TTL level Schmitt-trigger input pin
W83L517D
Version 0.6
1.1 LPC Interface
SYMBOL
PIN
CLKIN
6
PME#
PCICLK
LDRQ#
SERIRQ
7
12
13
11
LAD[0:3]
LFRAME#
LRESET#
PDCTL#
14,
16-18
19
8
9
I/O
INt
OD12
INtsp3
O12tp3
I/OD12t
I/O12tp3
FUNCTION
System clock input. According to the input frequency 24MHz or
48MHz, it is selectable through register. Default is 24MHz
input.
Generated PME event.
PCI clock input.
Encoded DMA Request signal.
Serial IRQ input/Output.; Support both Continuous and Quiet
modes.
These signal lines communicate address, control, and data
information over the LPC bus between a host and a peripheral.
INtsp3
INtsp3
INtsp3
Indicates start of a new cycle or termination of a broken cycle.
Reset signal. It can connect to PCIRST# signal on the host.
Hardware power down input pin for chip power down.
Programmable control by registers.
5 Publication Release Date: Apr. 2000
Revision 0.60

12 Page





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